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IEEE Transactions on Applied Superconductivity

RSQO asynchronous serial multiplier and spreading codes generator for multiuser detector

Anna Kidiyarova-Shevchenko, K. Yu. Platov, E. Tolkacheva, Irina Kataeva

Published Jun 1, 2003• 8 citations
Publisher

Abstract

Serial multiplier and serial spreading code generators are vital elements of the RSFQ multiuser detector. We have designed different versions of both circuits to achieve maximum speed and at the same time minimize Josephson junction count. Comparison of different serial multipliers architectures supporting signed multiplication favored for asynchronous shifting over zero circuits based on carry save adder and co-flow distribution of the partial product and the clock. A 25-bit spreading code generator supporting parallel input/output has been designed for 4 kA/cm/sup 2/ (TRW) and for 1 kA/cm/sup 2/ (HYPRES) processes. The corresponding maximum simulated clock speed of 52 GHz and 26 GHz and effective device area of 1/spl times/0.12 mm/sup 2/ and 1.9/spl times/0.2 mm/sup 2/.

DOI
10.1109/tasc.2003.813889

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IEEE Transactions on Applied Superconductivity•Jun 1, 1999•40 citations
Serial multiplier and serial spreading code generators are vital elements of the RSFQ multiuser detector. We have designed different versions of both circuits to achieve maximum speed and at the same time minimize Josephson junction count. Comparison of different serial multipliers architectures supporting signed multiplication favored for asynchronous shifting over zero circuits based on carry save adder and co-flow distribution of the partial product and the clock. A 25-bit spreading code generator supporting parallel input/output has been designed for 4 kA/cm/sup 2/ (TRW) and for 1 kA/cm/sup 2/ (HYPRES) processes. The corresponding maximum simulated clock speed of 52 GHz and 26 GHz and effective device area of 1/spl times/0.12 mm/sup 2/ and 1.9/spl times/0.2 mm/sup 2/.
This work presents the design of RSFQ parallel multiplier suitable for implementation of the superconducting digital signal processor for interference cancellation in 3G cellular systems. We have designed the parallel multiplier which consists of N M-bits serial adders based on the T1 cells for M ×N sign multiplication. This multiplier consumes 74×M×N Josephson junctions. The 2-bit and 4-bit parallel multipliers have been designed for TRWs 8 kA/cm2 process. The maximum VHDL simulated clock speed and one bit effective area are 39 GHz and 300 × 300 μm2 correspondingly.
We have designed and RSFQ multiplier-accumulator, the central component of our decimation digital filter. The circuit consists of 38 synchronous RSFQ cells of six types arranged into a rectangular systolic array fed by one parallel input and one serial input. Timing is based on counter-flow clock distribution scheme with simulated maximum clock frequency of 11 GHz. The circuit, fabricated at Hypres, Inc., contains 1100 Josephson junctions, has power consumption less than 0.2 mW, and area less than 2.5 mm/sup 2/. The multiplier-accumulator has been tested at low frequency demonstrating full functionality and stable operation over a 24 hour testing period. This four-bit multiplier accumulator is one of the largest reported RSFQ circuits verified experimentally to date.
We have designed a Rapid Single-Flux-Quantum (RSFQ) bit-serial real-time pipeline multiplier for digital signal processing (DSP) applications. A single-bit module of this multiplier consists of 96 Josephson junctions and uses a B-flip-flop-based carry-save adder (CSA). For HYPRES' standard 1-kA/cm/sup 2/ Nb process with 3.5 /spl mu/m-diameter Josephson junctions the module occupies all area of 350/spl times/600 /spl mu/m/sup 2/. Simulations show that the circuit should dissipate 28 /spl mu/W of power at 2.6 mV dc supply voltage and operate at frequencies of up to 25 GHz. We have successfully tested all cells of the module and verified correct operation of a simplified version of the module at low frequencies. According to numerical simulations, the speed of the multiplier is limited by the CSA. In order to overcome this bottleneck we have developed a concept of a fast carry-save pipeline adder based on XOR gates which uses an RSFQ-specific algorithm for carry bit calculation.>
We have designed and successfully tested at low speed a rapid single flux quantum signed serial multiplier-accumulator with target clock frequency 20 GHz. Each bit slice of the device consists of 106 Josephson junctions and 90 resistors. It consumes 22 mA of current and occupies 0.3 mm/sup 2/. The accumulator of the developed multiplier makes two (rather than three) primitive operations per cycle without any additional overheads. This makes it fast and very robust. In particular, /spl plusmn/18% bias supply margins have been measured in a four-slice multiplier. This is our first device where superconductor microstrip lines (MSLs) have been routinely used. The MSL interfaces introduce some overhead but it is compensated by the simplicity of the design procedure.
We will discuss the microarchitecture, design, and testing of the first 8 × 8-bit (by modulo 256) parallel carry-save RSFQ multiplier implemented using the ISTEC 10- kA/cm21.0-μm fabrication technology. Partial products are asynchronously generated and sent to the reduction stage at the internal “hardwired” rate of 80 GHz. The 8 × 8-bit RSFQ multiplier uses a two-level parallel carry-save reduction tree that significantly reduces the multiplier latency. The 80-GHz carry-save reduction is implemented with asynchronous data-driven wave-pipelined [4:2] compressors built with toggle flip-flop cells. The design has mostly regular layout with both local and global connections between modules. The multiplier core (without SFQ-to-DC and DC-to-SFQ converters) has 5948 Josephson junctions occupying the area of 3.5 mm2. The multiplier is designed with the target operation frequency of 20 GHz and has the latency of 447 ps at the bias voltage of 2.5 mV. Despite some challenges due to fabrication process parameter variations and flux trapping, the multiplier chip was fabricated and successfully tested for the vast majority of test vectors by the Stony Brook designers with the assistance of colleagues from Yokohama National University in February 2012. While multiplier test operations were generated at low frequency, each of these operations was executed at the “hardwired” rate of 80 GHz. The fabricated chip operated with the measured DC bias margins of ±5%.
We present a design for parallel pipelined carry-lookahead Kogge-Stone 32and 64-bit integer adders with the traditional concurrent flow timing scheme, and the results of its gate-level logical simulation using a VHDL model, with parameters reduced from the physical-level simulation of RSFQ cells. The design uses only five different types of bit processing blocks and is easily scalable to any length of the operands. The multi-pulse logic representation together with interchanging logical polarity between pipeline stages is used to simplify the design of the blocks, which contain only two types of clocked RSFQ gates: an inverter and a D-flip-flop. Simulations show that in the absence of thermal fluctuations and random parameter spread the clock frequency of the adder implemented in the projected 0.8 /spl mu/m Nb-trilayer technology could be as high as 150 GHz. However, an approximate account of these factors shows that in order to achieve a 99% adder fabrication yield and a 10/sup -25/ adder error rate the maximal frequency should be reduced to 60 GHz for 1.5% Josephson junction spread and to 52 GHz for 3% spread. Adder latency is close to 260 ps for 32 bits and 320 ps for 64 bits. We plan to re-design the adders to increase their speed.