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IEEE Transactions on Applied Superconductivity

Case study in RSFQ design: fast pipelined parallel adder

P. Bunyk, P. Litskevitch

Published Jun 1, 1999• 40 citations
Publisher

Abstract

We present a design for parallel pipelined carry-lookahead Kogge-Stone 32and 64-bit integer adders with the traditional concurrent flow timing scheme, and the results of its gate-level logical simulation using a VHDL model, with parameters reduced from the physical-level simulation of RSFQ cells. The design uses only five different types of bit processing blocks and is easily scalable to any length of the operands. The multi-pulse logic representation together with interchanging logical polarity between pipeline stages is used to simplify the design of the blocks, which contain only two types of clocked RSFQ gates: an inverter and a D-flip-flop. Simulations show that in the absence of thermal fluctuations and random parameter spread the clock frequency of the adder implemented in the projected 0.8 /spl mu/m Nb-trilayer technology could be as high as 150 GHz. However, an approximate account of these factors shows that in order to achieve a 99% adder fabrication yield and a 10/sup -25/ adder error rate the maximal frequency should be reduced to 60 GHz for 1.5% Josephson junction spread and to 52 GHz for 3% spread. Adder latency is close to 260 ps for 32 bits and 320 ps for 64 bits. We plan to re-design the adders to increase their speed.

DOI
10.1109/77.783835

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IEICE Transactions on Electronics•Jan 1, 2016•12 citations
We present a design for parallel pipelined carry-lookahead Kogge-Stone 32and 64-bit integer adders with the traditional concurrent flow timing scheme, and the results of its gate-level logical simulation using a VHDL model, with parameters reduced from the physical-level simulation of RSFQ cells. The design uses only five different types of bit processing blocks and is easily scalable to any length of the operands. The multi-pulse logic representation together with interchanging logical polarity between pipeline stages is used to simplify the design of the blocks, which contain only two types of clocked RSFQ gates: an inverter and a D-flip-flop. Simulations show that in the absence of thermal fluctuations and random parameter spread the clock frequency of the adder implemented in the projected 0.8 /spl mu/m Nb-trilayer technology could be as high as 150 GHz. However, an approximate account of these factors shows that in order to achieve a 99% adder fabrication yield and a 10/sup -25/ adder error rate the maximal frequency should be reduced to 60 GHz for 1.5% Josephson junction spread and to 52 GHz for 3% spread. Adder latency is close to 260 ps for 32 bits and 320 ps for 64 bits. We plan to re-design the adders to increase their speed.
In this paper, we discuss the architecture, design, and testing of the first 16-bit asynchronous wave-pipelined sparse-tree superconductor rapid single flux quantum adder implemented using the ISTEC 10 kA/cm2ADP2.1 fabrication process. Compared to the Kogge-Stone adder, our parallel-prefix sparse-tree adder has better energy efficiency with significantly reduced complexity (at the expense of latency) and almost no decrease in operation frequency. The 16-bit adder core (without SFQ-to-dc and dc-to-SFQ converters) has 9941 Josephson junctions occupying an area of 8.5 mm2. It is designed for the target operation frequency of 30 GHz with the expected latency of 352 ps at the bias voltage of 2.5 mV. The adder chip was fabricated and successfully tested at low frequency for all test patterns with measured bias margins of +9.8%/-10.7%.
As part of the effort to develop a superconductive microprocessor, we constructed a rapid single flux quantum (RSFQ) 4-bit arithmetic and logic unit (ALU) in a pipelined structure. To speed up the circuit, we used a forward clocking scheme. The 4-bit ALU consisted of ten RSFQ Half Adders, four 2 /spl times/ 2 switches, and several D flip-flops. By commutating output ports of the half adder, we were able to produce AND, OR, XOR, and ADD functions. The 4-bit ALU was fabricated using the Korea Photonics Technology Institute's ten-level 1.0 kA/cm/sup 2/ Nb process. The size of the ALU was 3.0 mm /spl times/ 1.5 mm, fitting in a 5 mm /spl times/ 5 mm chip. The fabricated 1-bit ALU block was successfully tested at up to a 40 GHz clock frequency. The complete 4-bit ALU operated correctly at up to a 5 GHz clock frequency.
The authors consider the design of a binary carry full-adder cell using the logic gates and buffers belonging to the rapid single-flux-quantum (RSFQ) logic family. They have taken advantage of the unique properties of RSFQ pulse logic to realize two designs: one using two logic gates and a toggle flip-flop in two stages of logic, the other using two logic gates in one stage of logic. They have determined the parameter margins of the two full-adder cells and optimized them to obtain critical margins approaching +or-30%. Simulations of the full-adder cells have revealed critical delays and maximum clock frequencies of 58 ps and 17 GHz and 33 ps and 30 GHz, respectively.>
We will discuss the microarchitecture, design, and testing of the first 8 × 8-bit (by modulo 256) parallel carry-save RSFQ multiplier implemented using the ISTEC 10- kA/cm21.0-μm fabrication technology. Partial products are asynchronously generated and sent to the reduction stage at the internal “hardwired” rate of 80 GHz. The 8 × 8-bit RSFQ multiplier uses a two-level parallel carry-save reduction tree that significantly reduces the multiplier latency. The 80-GHz carry-save reduction is implemented with asynchronous data-driven wave-pipelined [4:2] compressors built with toggle flip-flop cells. The design has mostly regular layout with both local and global connections between modules. The multiplier core (without SFQ-to-DC and DC-to-SFQ converters) has 5948 Josephson junctions occupying the area of 3.5 mm2. The multiplier is designed with the target operation frequency of 20 GHz and has the latency of 447 ps at the bias voltage of 2.5 mV. Despite some challenges due to fabrication process parameter variations and flux trapping, the multiplier chip was fabricated and successfully tested for the vast majority of test vectors by the Stony Brook designers with the assistance of colleagues from Yokohama National University in February 2012. While multiplier test operations were generated at low frequency, each of these operations was executed at the “hardwired” rate of 80 GHz. The fabricated chip operated with the measured DC bias margins of ±5%.
Abstract: We have developed and experimentally evaluated at high-speed, a complete set of arithmetic circuits (multiply, add, and accumulate) for high performance digital signal processing (DSP). These circuits take advantage of the unique features of the Rapid Single-Flux Quantum (RSFQ) logic/memory family, including fusion of logic and memory functions at the gate level, pulse representation of clock and data, and the ability to maintain inter cell propagation delays using Josephson transmission lines (JTLs). The circuits developed have been successfully used in the implementation of a serial radix 2 butterfly, a decimation digital filter, and of an arithmetic unit for digital beam forming. The 8×8-bit RSFQ multiplier uses a two- level parallel carry- save reduction tree that significantly reduces the multiplier latency. The 80-GHz carry-save reduction is implemented with asynchronous data-driven wave pipelined [4:2] compressors built with toggle flip-flop cells.
A rapid single-flux-quantum (RSFQ) 4-bit bit-slice multiplier is proposed. A new systolic-like multiplication algorithm suitable for RSFQ implementation is developed. The multiplier is designed using the cell library for AIST 10-kA/cm2 1.0-μm fabrication technology (ADP2). Concurrent flow clocking is used to design a fully pipelined RSFQ logic design. A 4n x 4n-bit multiplier consists of 2n + 17 stages. For verifying the algorithm and the logic design, a physical layout of the 8 x 8-bit multiplier has been designed with target operating frequency of 50 GHz and simulated. It consists of 21 stages and 11, 488 Josephson junctions. The simulation results show correct operation up to 62.5 GHz.