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IEEE Transactions on Applied Superconductivity

RSFQ Signed Serial Multiplier–Accumulator

Nikolai Joukov, M.S. Tivari, Vasili K. Semenov

Published Mar 1, 2005• 5 citations
Publisher

Abstract

We have designed and successfully tested at low speed a rapid single flux quantum signed serial multiplier-accumulator with target clock frequency 20 GHz. Each bit slice of the device consists of 106 Josephson junctions and 90 resistors. It consumes 22 mA of current and occupies 0.3 mm/sup 2/. The accumulator of the developed multiplier makes two (rather than three) primitive operations per cycle without any additional overheads. This makes it fast and very robust. In particular, /spl plusmn/18% bias supply margins have been measured in a four-slice multiplier. This is our first device where superconductor microstrip lines (MSLs) have been routinely used. The MSL interfaces introduce some overhead but it is compensated by the simplicity of the design procedure.

DOI
10.1109/tasc.2005.844189

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A design of a 32 × 32-bit 4-bit bit-slice integer multiplier for rapid single-flux quantum microprocessors is shown. The multiplier carries out both signed and unsigned multiplication. It is designed with synchronous concurrent-flow clocking and target frequency of 50 GHz using the AIST 1.0-μm Nb/AlOx/Nb, nine-layer advanced process 2 fabrication technology with a critical current density of 10 kA/cm2. It consists of 56 885 Josephson junctions. The area is 12.00 × 6.65 mm2. The simulation results show correct operation with frequency of 50 GHz at the dc bias voltage of 2.5 mV. The throughput is 3.125 × 109multiplications per second.
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Serial multiplier and serial spreading code generators are vital elements of the RSFQ multiuser detector. We have designed different versions of both circuits to achieve maximum speed and at the same time minimize Josephson junction count. Comparison of different serial multipliers architectures supporting signed multiplication favored for asynchronous shifting over zero circuits based on carry save adder and co-flow distribution of the partial product and the clock. A 25-bit spreading code generator supporting parallel input/output has been designed for 4 kA/cm/sup 2/ (TRW) and for 1 kA/cm/sup 2/ (HYPRES) processes. The corresponding maximum simulated clock speed of 52 GHz and 26 GHz and effective device area of 1/spl times/0.12 mm/sup 2/ and 1.9/spl times/0.2 mm/sup 2/.
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