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IEEE Transactions on Applied Superconductivity

32-Bit 4 × 4 Bit-Slice RSFQ Matrix Multiplier

Guang-Ming Tang, Pei-Yao Qu, Xiaochun Ye, Dongrui Fan, Ninghui Sun

Published May 18, 2018• 8 citations
Publisher

Abstract

A 32-bit 4 × 4 bit-slice rapid single-flux-quantum (RSFQ) matrix multiplier is proposed. The multiplier mainly consists of bit-slice multipliers and bit-slice adders. The multiplication of unsigned integer matrices is implemented by control signals. The matrix multiplier used synchronous concurrent-flow clocking. The results show that a 16-bit bit-slice processing has the least latency at 10 GHz.

DOI
10.1109/tasc.2018.2836954

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A 32-bit 4 × 4 bit-slice rapid single-flux-quantum (RSFQ) matrix multiplier is proposed. The multiplier mainly consists of bit-slice multipliers and bit-slice adders. The multiplication of unsigned integer matrices is implemented by control signals. The matrix multiplier used synchronous concurrent-flow clocking. The results show that a 16-bit bit-slice processing has the least latency at 10 GHz.
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A design of a 32 × 32-bit 4-bit bit-slice integer multiplier for rapid single-flux quantum microprocessors is shown. The multiplier carries out both signed and unsigned multiplication. It is designed with synchronous concurrent-flow clocking and target frequency of 50 GHz using the AIST 1.0-μm Nb/AlOx/Nb, nine-layer advanced process 2 fabrication technology with a critical current density of 10 kA/cm2. It consists of 56 885 Josephson junctions. The area is 12.00 × 6.65 mm2. The simulation results show correct operation with frequency of 50 GHz at the dc bias voltage of 2.5 mV. The throughput is 3.125 × 109multiplications per second.
A rapid single-flux-quantum (RSFQ) 4-bit bit-slice multiplier is proposed. A new systolic-like multiplication algorithm suitable for RSFQ implementation is developed. The multiplier is designed using the cell library for AIST 10-kA/cm2 1.0-μm fabrication technology (ADP2). Concurrent flow clocking is used to design a fully pipelined RSFQ logic design. A 4n x 4n-bit multiplier consists of 2n + 17 stages. For verifying the algorithm and the logic design, a physical layout of the 8 x 8-bit multiplier has been designed with target operating frequency of 50 GHz and simulated. It consists of 21 stages and 11, 488 Josephson junctions. The simulation results show correct operation up to 62.5 GHz.
A 4-bit bit-slice arithmetic logic unit (ALU) for 32-bit rapid single-flux-quantum microprocessors was demonstrated. The proposed ALU covers all of the ALU operations for the MIPS32 instruction set. It processes bit-sliced 32-bit data that are divided into eight slices of 4 bits. The bit-slice approach simplifies the circuit structure and reduces the hardware cost. The ALU uses synchronous concurrent-flow clocking and consists of eight pipeline stages. It was implemented using the 1.0-μm Nb/AlOx/Nb nine-layer advanced process 2 (ADP2) with a critical current density of 10 kA/cm2, and fabricated by National Institute of Advanced Industrial Science and Technology (AIST). It consists of 3481 Josephson junctions with an area of 3.09 × 1.66 mm2. It achieved the target frequency of 50 GHz and a latency of 524 ps for a 32-bit operation, at the designed DC bias voltage of 2.5 mV, via precise control of interconnect delays and clock distribution. Furthermore, it achieved a throughput of 6.25 × 10932-bit operations per second. All the correct ALU operations with measured DC bias voltage margins of around 10% at 50 GHz were successfully obtained. The proposed ALU can be used for any 4n-bit processing.