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The Japan Society of Applied Physics

Design and evaluation of memory cells driven with low currents for SFQ pulse-deriven memory

H. Fujisawa, Yuto Takeshita, Kento Kato, Masayuki Higashi, Daiki Hasegawa, Feng Li, Masamitsu Tanaka, Taro Yamashita, Akira Fujimaki

Published Jan 26, 2021• 0 citations
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We propose a new cryogenic high-speed and low-power matrix memory required for achieving a high-performance superconductor computing system. The memory cell is based on the 0-π SQUID with conventional Josephson junctions (0-junctions) and a π-shifted ferromagnetic Josephson junction (π-junction). The memory state is stored in the form of two stable states in the 0-π SQUID. The π shift feature of the π-junction eliminates the need for any bias current or magnetic field for the formation of two states, i.e., the memory is non-volatile. In this memory, an impulse-shaped voltage signal generated in single-flux-quantum (SFQ) circuits is used for the write and read operations of the memory state. By using the pulses propagating in passive transmission lines, high-speed and low-power operation can be achieved because a recharging process determining the operation speed and the dominant energy consumption can be eliminated. We fabricated the 0-π SQUID-based pulse-driven memory cells with an SFQ driver. From the static characteristics, we confirmed that the current needed for rewriting can be sufficiently reduced. In addition, we successfully demonstrated the correct write operation in the memory cell by the SFQ pulse train transmitted from the SFQ driver via the passive transmission line.
Abstract One of the main challenges for single flux quantum (SFQ) technology to successfully implement a microprocessor is to have a compact and robust on-chip memory that can be used for register files and cache memory. In this context, we designed high capacity destructive readout (HC-DRO) cells. The design is based on our insight that each cell can store more than one SFQ pulse with the same area footprint of a regular DRO cell. In our current design, we demonstrate a single HC-DRO cell that can store up to three SFQ pulses thereby enabling us to store the equivalent of two bits of memory in a single cell. We have designed a register file (RF) architecture for a microprocessor and used the HC-DRO cells to reduce the Josephson junction count required for its implementation. The RF architecture presented in this work can also be used for implementing cache memories. We also demonstrate the benefits of doubling the storage density with HC-DRO cells by designing a 2-bit branch predictor circuit block for a 5-stage pipeline microprocessor that dramatically improves the cycles per instruction metric of an SFQ based microprocessor. All the design details are presented in the paper by verifying the design concepts through JSIM simulations and Verilog simulations.
We investigated the hardware implementation of an area-efficient superconducting lookup table (LUT) based on a single flux quantum (SFQ) logic by using a newly proposed small memory cell. The memory cell is composed of a nondestructive read-out (NDRO) flip-flop with input circuits that convert the input dc current to an SFQ pulse signal. The datum can be written to the selected memory cell in the 2-D memory cell array by applying bothx- andy-directional dc control currents. The data stored in the memory cell array can be reset simultaneously by applying a dc current to a common reset line. By employing the new memory cell, wiring for reconfiguring the data and resetting the memory cell array can be drastically simplified compared to that of the conventional SFQ LUT. We implemented and tested the memory cell and confirmed the correct operation with wide dc bias and input-current margins. We designed the 16-b LUT using the designed memory cells. The circuit area and the number of Josephson junctions of the 16-b LUT is reduced by approximately 24 and 41%, respectively, compared to those of the LUT based on the conventional architecture. We experimentally obtained the correct operation and reconfiguration of the 4-b LUT that uses the new memory cells with a normalized bias margin of –22 to +7%.