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IEEE Transactions on Applied Superconductivity

High-Speed Memory Driven by SFQ Pulses Based on 0-π SQUID

Yuto Takeshita, Feng Li, Daiki Hasegawa, Kyosuke Sano, Masamitsu Tanaka, Taro Yamashita, Akira Fujimaki

Published Feb 20, 2021• 26 citations
Publisher

Abstract

We propose a new cryogenic high-speed and low-power matrix memory required for achieving a high-performance superconductor computing system. The memory cell is based on the 0-π SQUID with conventional Josephson junctions (0-junctions) and a π-shifted ferromagnetic Josephson junction (π-junction). The memory state is stored in the form of two stable states in the 0-π SQUID. The π shift feature of the π-junction eliminates the need for any bias current or magnetic field for the formation of two states, i.e., the memory is non-volatile. In this memory, an impulse-shaped voltage signal generated in single-flux-quantum (SFQ) circuits is used for the write and read operations of the memory state. By using the pulses propagating in passive transmission lines, high-speed and low-power operation can be achieved because a recharging process determining the operation speed and the dominant energy consumption can be eliminated. We fabricated the 0-π SQUID-based pulse-driven memory cells with an SFQ driver. From the static characteristics, we confirmed that the current needed for rewriting can be sufficiently reduced. In addition, we successfully demonstrated the correct write operation in the memory cell by the SFQ pulse train transmitted from the SFQ driver via the passive transmission line.

DOI
10.1109/tasc.2021.3060351

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A new design concept for the Josephson-junction random access memory (RAM) has been developed. In contrast to previous RAMs based on single flux quantization (SFQ), in our system READ and WRITE operations employ ballistic transfer of SFQ pulses along bit lines (either Josephson transmission lines, or passive superconducting microstrip lines, or their combination). The basic memory cells are the single-junction SQUIDs, connected serially by the bit lines and inductively coupled to word lines. READ and WRITE operations are performed by sending SFQ pulses in appropriate directions along bit lines, and DC currents of appropriate polarity into word lines. This approach allows design of very dense memories with n/spl les/2 Josephson junctions per bit, memory cell area smaller than 80 /spl lambda//sup 2/ (where /spl lambda/ is the minimum feature size), and the critical parameter margin well above /spl plusmn/20%. In this paper we present the general structure of the RSFQ RAM, as well as design and results of testing of the basic memory cell and decoder circuitry using Hypres' 3.5-/spl mu/m, 1-kA/cm/sup 2/ Nb-trilayer technology.>
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