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Towards ultra-high fidelity quantum operations: SQiSW gate as a native two-qubit gate

Cupjin Huang, Dawei Ding, Feng Wu, Linghang Kong, Fang Zhang, Xiaotong Ni, Yaoyun Shi, Hui‐Hai Zhao, Jianxin Chen

Published May 13, 2021• 4 citations
OpenAlex

Abstract

We propose $\mathrm{SQiSW}$, the matrix square root of the standard $\mathrm{iSWAP}$ gate, as a native two-qubit gate for superconducting quantum computing. We show numerically that it has potential for an ultra-high fidelity implementation as its gate time is half of that of $\mathrm{iSWAP}$, but at the same time it possesses powerful information processing capabilities in both the compilation of arbitrary two-qubit gates and the generation of large-scale entangled W-like states. Even though it is half of an $\mathrm{iSWAP}$ gate, its capabilities surprisingly rival and even surpass that of $\mathrm{iSWAP}$ or other incumbent native two-qubit gates such as $\mathrm{CNOT}$. To complete the case for its candidacy, we propose a detailed compilation, calibration and benchmarking framework. In particular, we propose a variant of randomized benchmarking called interleaved fully randomized benchmarking (iFRB) which provides a general and unified solution for benchmarking non-Clifford gates such as $\mathrm{SQiSW}$. For the reasons above, we believe that the $\mathrm{SQiSW}$ gate is worth further study and consideration as a native two-qubit gate for both fault-tolerant and noisy intermediate-scale quantum (NISQ) computation.

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A quantum instruction set is where quantum hardware and software meet. We develop characterization and compilation techniques for non-Clifford gates to accurately evaluate its designs. Applying these techniques to our fluxonium processor, we show that replacing the iSWAP gate by its square root SQiSW leads to a significant performance boost at almost no cost. More precisely, on SQiSW we measure a gate fidelity of up to 99.72% and averaging at 99.31%, and realize Haar random two-qubit gates with an average fidelity of 96.38%. This is an average error reduction of 41% for the former and a 50% reduction for the latter compared to using iSWAP on the same processor.

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We propose SQiSW\mathrm{SQiSW}SQiSW, the matrix square root of the standard iSWAP\mathrm{iSWAP}iSWAP gate, as a native two-qubit gate for superconducting quantum computing. We show numerically that it has potential for an ultra-high fidelity implementation as its gate time is half of that of iSWAP\mathrm{iSWAP}iSWAP, but at the same time it possesses powerful information processing capabilities in both the compilation of arbitrary two-qubit gates and the generation of large-scale entangled W-like states. Even though it is half of an iSWAP\mathrm{iSWAP}iSWAP gate, its capabilities surprisingly rival and even surpass that of iSWAP\mathrm{iSWAP}iSWAP or other incumbent native two-qubit gates such as CNOT\mathrm{CNOT}CNOT. To complete the case for its candidacy, we propose a detailed compilation, calibration and benchmarking framework. In particular, we propose a variant of randomized benchmarking called interleaved fully randomized benchmarking (iFRB) which provides a general and unified solution for benchmarking non-Clifford gates such as SQiSW\mathrm{SQiSW}SQiSW. For the reasons above, we believe that the SQiSW\mathrm{SQiSW}SQiSW gate is worth further study and consideration as a native two-qubit gate for both fault-tolerant and noisy intermediate-scale quantum (NISQ) computation.
The primary objective of quantum circuit synthesis is to efficiently and accurately realize specific quantum algorithms or operations utilizing a predefined set of quantum gates, while also optimizing the circuit size. It holds a pivotal position in Noisy Intermediate-Scale Quantum (NISQ) computation. Historically, most synthesis efforts have predominantly utilized CNOT or CZ gates as the 2-qubit gates. However, the SQiSW gate, also known as the square root of iSWAP gate, has garnered considerable attention due to its outstanding experimental performance with low error rates and high efficiency in 2-qubit gate synthesis. In this paper, we investigate the potential of the SQiSW gate in various synthesis problems by utilizing only the SQiSW gate along with arbitrary single-qubit gates, while optimizing the overall circuit size. For exact synthesis, the upper bound of SQiSW gates to synthesize arbitrary 3-qubit and n -qubit gates are 24 and 139 192 4 n ( 1 + o ( 1 ) ) respectively, which relies on the properties of SQiSW gate in Lie theory and Quantum Shannon Decomposition. We also introduce an exact synthesis scheme for Toffoli gate using only 8 SQiSW gates, which is grounded in numerical observation. More generally, with respect to numerical approximations, we provide a theoretical analysis of a pruning algorithm to reduce the size of the searching space in numerical experiment to 1 12 + o ( 1 ) of previous size, helping us reach the result that 11 SQiSW gates are enough in arbitrary 3-qubit gates synthesis up to an acceptable numerical error.
The Berkeley gate is a high-performance, two-qubit entangling operation with particular potential for quantum error correction and fault-tolerant protocols. However, harnessing this potential on current noisy intermediate-scale quantum (NISQ) processors, requires efficient compilation and robust performance under realistic noise conditions. In this work, we demonstrate a hardware-efficient implementation of the Berkeley gate on a superconducting quantum processor. Using quantum process tomography (QPT), we experimentally characterize its performance and benchmark it against a noiseless quantum simulator to evaluate its practical reliability in the NISQ era. Experimental measurements confirm the gate's correct logical action, producing the target partially entangled state with a subspace confinement probability of [Formula: see text] on real quantum hardware compared to 100% in quantum simulation. Results from QPT experiments show a simulated process fidelity of [Formula: see text], while the experimental process fidelity on hardware is [Formula: see text]. The observed discrepancy is analyzed in the context of device-specific noise sources, including qubit relaxation, dephasing, and state preparation and measurement (SPAM) errors. Our work provides a concrete fidelity benchmark for the Berkeley gate on superconducting hardware and quantify the impact of realistic noise on a non-trivial two-qubit operation, supporting its use in near-term algorithmic and error-correction applications.
Abstract Universal quantum computation will require qubit technology based on a scalable platform1, together with quantum error correction protocols that place strict limits on the maximum infidelities for one- and two-qubit gate operations2, 3. Although various qubit systems have shown high fidelities at the one-qubit level4–10, the only solid-state qubits manufactured using standard lithographic techniques that have demonstrated two-qubit fidelities near the fault-tolerance threshold6 have been in superconductor systems. Silicon-based quantum dot qubits are also amenable to large-scale fabrication and can achieve high single-qubit gate fidelities (exceeding 99.9 per cent) using isotopically enriched silicon11, 12. Two-qubit gates have now been demonstrated in a number of systems13–15, but as yet an accurate assessment of their fidelities using Clifford-based randomized benchmarking, which uses sequences of randomly chosen gates to measure the error, has not been achieved. Here, for qubits encoded on the electron spin states of gate-defined quantum dots, we demonstrate Bell state tomography with fidelities ranging from 80 to 89 per cent, and two-qubit randomized benchmarking with an average Clifford gate fidelity of 94.7 per cent and an average controlled-rotation fidelity of 98 per cent. These fidelities are found to be limited by the relatively long gate times used here compared with the decoherence times of the qubits. Silicon qubit designs employing fast gate operations with high Rabi frequencies16, 17, together with advanced pulsing techniques18, should therefore enable much higher fidelities in the near future.
High-quality two-qubit gate operations are crucial for scalable quantum information processing. Often, the gate fidelity is compromised when the system becomes more integrated. Therefore, a low-error-rate, easy-to-scale two-qubit gate scheme is highly desirable. Here, we experimentally demonstrate a new two-qubit gate scheme that exploits fixed-frequency qubits and a tunable coupler in a superconducting quantum circuit. The scheme requires less control lines, reduces cross talk effect, and simplifies calibration procedures, yet produces a controlled-Z gate in 30 ns with a high fidelity of 99.5%, derived from the interleaved randomized benchmarking method. Error analysis shows that gate errors are mostly coherence limited. Our demonstration paves the way for large-scale implementation of high-fidelity quantum operations.
Noisy intermediate-scale quantum computers (NISQ) have demonstrated superior performance compared to conventional computing schemes. Nonetheless, errors associated with two-qubit entangling gates remain a substantial obstacle in fully harnessing the potential of current superconducting quantum computers. The achievement of quantum computation and quantum information processing critically depends on the presence of entangled states. These states are indispensable for quantum computers to surpass classical computers in terms of computational power. This paper presents a comprehensive characterization of a two-qubit entangling gate, known as Dagwood Bumstead (DB) gate, to investigate the challenges posed by errors in the DB gate on NISQ devices. Firstly, we propose a scheme for the realization of the DB gate using two capacitively coupled Josephson Superconducting qubits, based on the experimental setup carried out in Bialczak et al. (2010). The gate’s performance is fully described through quantum process tomography (QPT) and quantum state tomography (QST) experiments conducted in three different environments: noisy, noiseless, and on a real IBM quantum computer. The process fidelity of the DB gate is measured to be 0.8069705, and the state fidelity is determined to be 0.8858750. This study offers valuable insights into the performance of the DB gate on a NISQ device, showcasing its potential for executing intricate algorithms and operations on an authentic quantum computer.
A quantum instruction set is where quantum hardware and software meet. We develop characterization and compilation techniques for non-Clifford gates to accurately evaluate its designs. Applying these techniques to our fluxonium processor, we show that replacing the iSWAP gate by its square root SQiSW leads to a significant performance boost at almost no cost. More precisely, on SQiSW we measure a gate fidelity of up to 99.72% and averaging at 99.31%, and realize Haar random two-qubit gates with an average fidelity of 96.38%. This is an average error reduction of 41% for the former and a 50% reduction for the latter compared to using iSWAP on the same processor.