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arXiv:2412.14828 · Quantum

Quantum circuit synthesis with SQiSW

Jialiang Tang, Jiajia Zhang, Xiaoming Sun

Published Oct 20, 2025• 0 citations
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Abstract

The primary objective of quantum circuit synthesis is to efficiently and accurately realize specific quantum algorithms or operations utilizing a predefined set of quantum gates, while also optimizing the circuit size. It holds a pivotal position in Noisy Intermediate-Scale Quantum (NISQ) computation. Historically, most synthesis efforts have predominantly utilized CNOT or CZ gates as the 2-qubit gates. However, the SQiSW gate, also known as the square root of iSWAP gate, has garnered considerable attention due to its outstanding experimental performance with low error rates and high efficiency in 2-qubit gate synthesis. In this paper, we investigate the potential of the SQiSW gate in various synthesis problems by utilizing only the SQiSW gate along with arbitrary single-qubit gates, while optimizing the overall circuit size. For exact synthesis, the upper bound of SQiSW gates to synthesize arbitrary 3-qubit and n -qubit gates are 24 and 139 192 4 n ( 1 + o ( 1 ) ) respectively, which relies on the properties of SQiSW gate in Lie theory and Quantum Shannon Decomposition. We also introduce an exact synthesis scheme for Toffoli gate using only 8 SQiSW gates, which is grounded in numerical observation. More generally, with respect to numerical approximations, we provide a theoretical analysis of a pruning algorithm to reduce the size of the searching space in numerical experiment to 1 12 + o ( 1 ) of previous size, helping us reach the result that 11 SQiSW gates are enough in arbitrary 3-qubit gates synthesis up to an acceptable numerical error.

DOI
10.22331/q-2025-10-20-1889

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The primary objective of quantum circuit synthesis is to efficiently and accurately realize specific quantum algorithms or operations utilizing a predefined set of quantum gates, while also optimizing the circuit size. It holds a pivotal position in Noisy Intermediate-Scale Quantum (NISQ) computation. Historically, most synthesis efforts have predominantly utilized CNOT or CZ gates as the 2-qubit gates. However, the SQiSW gate, also known as the square root of iSWAP gate, has garnered considerable attention due to its outstanding experimental performance with low error rates and high efficiency in 2-qubit gate synthesis. In this paper, we investigate the potential of the SQiSW gate in various synthesis problems by utilizing only the SQiSW gate along with arbitrary single-qubit gates, while optimizing the overall circuit size. For exact synthesis, the upper bound of SQiSW gates to synthesize arbitrary 3-qubit and n -qubit gates are 24 and 139 192 4 n ( 1 + o ( 1 ) ) respectively, which relies on the properties of SQiSW gate in Lie theory and Quantum Shannon Decomposition. We also introduce an exact synthesis scheme for Toffoli gate using only 8 SQiSW gates, which is grounded in numerical observation. More generally, with respect to numerical approximations, we provide a theoretical analysis of a pruning algorithm to reduce the size of the searching space in numerical experiment to 1 12 + o ( 1 ) of previous size, helping us reach the result that 11 SQiSW gates are enough in arbitrary 3-qubit gates synthesis up to an acceptable numerical error.
The current phase of quantum computing is in the Noisy Intermediate-Scale Quantum (NISQ) era. On NISQ devices, two-qubit gates such as CNOTs are much noisier than single-qubit gates, so it is essential to minimize their count. Quantum circuit synthesis is a process of decomposing an arbitrary unitary into a sequence of quantum gates, and can be used as an optimization tool to produce shorter circuits to improve overall circuit fidelity. However, the time-to-solution of synthesis grows exponentially with the number of qubits. As a result, synthesis is intractable for circuits on a large qubit scale. In this paper, we propose a hierarchical, block-by-block optimization framework, QGo, for quantum circuit optimization. Our approach allows an exponential cost optimization to scale to large circuits. QGo uses a combination of partitioning and synthesis: 1) partition the circuit into a sequence of independent circuit blocks; 2) re-generate and optimize each block using quantum synthesis; and 3) re-compose the final circuit by stitching all the blocks together. We perform our analysis and show the fidelity improvements in three different regimes: small-size circuits on real devices, medium-size circuits on noise simulations, and large-size circuits on analytical models. Using a set of NISQ benchmarks, we show that QGo can reduce the number of CNOT gates by 29.9% on average and up to 50% when compared with industrial compilers such as t|ket>. When executed on the IBM Athens system, shorter depth leads to higher circuit fidelity. We also demonstrate the scalability of our QGo technique to optimize circuits of 60+ qubits. Our technique is the first demonstration of successfully employing and scaling synthesis in the compilation toolchain for large circuits. Overall, our approach is robust for direct incorporation in production compiler toolchains.
The current phase of quantum computing is in the Noisy Intermediate-Scale Quantum (NISQ) era. On NISQ devices, two-qubit gates such as CNOTs are much noisier than single-qubit gates, so it is essential to minimize their count. Quantum circuit synthesis is a process of decomposing an arbitrary unitary into a sequence of quantum gates, and can be used as an optimization tool to produce shorter circuits to improve overall circuit fidelity. However, the time-to-solution of synthesis grows exponentially with the number of qubits. As a result, synthesis is intractable for circuits on a large qubit scale. In this paper, we propose a hierarchical, block-by-block optimization framework, QGo, for quantum circuit optimization. Our approach allows an exponential cost optimization to scale to large circuits. QGo uses a combination of partitioning and synthesis: 1) partition the circuit into a sequence of independent circuit blocks; 2) re-generate and optimize each block using quantum synthesis; and 3) re-compose the final circuit by stitching all the blocks together. We perform our analysis and show the fidelity improvements in three different regimes: small-size circuits on real devices, medium-size circuits on noise simulations, and large-size circuits on analytical models. Using a set of NISQ benchmarks, we show that QGo can reduce the number of CNOT gates by 29.9% on average and up to 50% when compared with industrial compilers such as t|ket>. When executed on the IBM Athens system, shorter depth leads to higher circuit fidelity. We also demonstrate the scalability of our QGo technique to optimize circuits of 60+ qubits. Our technique is the first demonstration of successfully employing and scaling synthesis in the compilation toolchain for large circuits. Overall, our approach is robust for direct incorporation in production compiler toolchains.
The quantum circuit synthesis problem bridges quantum algorithm design and quantum hardware implementation in the Noisy Intermediate-Scale Quantum (NISQ) era. In quantum circuit synthesis problems, diagonal unitary synthesis plays a crucial role due to its fundamental and versatile nature. Meanwhile, experimental results have shown that moderately approximating the original algorithm to conserve quantum resources can improve the fidelity of algorithms during quantum execution. Building on this insight, we propose a quantum circuit synthesis algorithm to design diagonal unitary implementations based on specified quantum resource limits. Our algorithm can synthesize diagonal unitary for quantum circuits with up to 15 qubits on an ordinary laptop. In algorithm efficiency, synthesizing an n-qubit unitary matrix with an exact algorithm requires 2n2^n2n CNOT gates as a baseline. Within the algorithm error $\varepsilon $ range of interest (0\%-12\%), our algorithm achieves a $3.2\varepsilon $ reduction in CNOT gates on average. In runtime, the algorithm efficiently performs, synthesizing 12-qubit diagonal unitary in an average of 6.57 seconds and 15-qubit in approximately 561.71 seconds.
In the near future of the noisy intermediate-scale quantum (NISQ) era, almost all quantum computing devices will be restricted to a specific fixed qubits connectivity architecture. Thus, the synthesis of quantum circuits with limited connectivity is urgent. We design quantum circuit synthesis algorithms for basic and essential synthesis problems, such as quantum state preparation, general unitary synthesis, and quantum isometries. For any architecture, the controlled not (cnot) count is at most 5/3 times the state-of-the-art result on complete-graph architecture. For some specific architectures, such as square-grid ones, the ratio is reduced to 1.126. The numerical simulation result is confirmatory of theoretical conclusions. Our algorithms significantly reduce by more than 5050%50 additional cnot count compared to mapping algorithms. These algorithms help to implement the larger-scale algorithm in the physics device. Our results illustrate that well-designed synthesis algorithms can mitigate the problem of limited qubit connectivity in the NISQ era and may suggest the design of large-scale quantum devices.
Multi-bit Toffoli gates form an essential quantum gate class for quantum algorithms. They should be efficiently decomposed into elementary single- or multi-qubit quantum gates, such as CNOT, T, and Hadarmard, for a scalable implementation of a quantum algorithm. We propose an engineering method for the practical synthesis of a multi-bit Toffoli gate. Two optimization models and their closed-form solutions are presented for optimal decomposition of the multi-bit Toffoli gate. These models are based on linearized multi-objective integer programming with parameters such as the number of target ancillae, ancillae states, and basis gates. The proposed method supports the systematic handling of quantum circuit constraints, including the total number of available qubits and maximum circuit depth, which depend on various quantum hardware specifications. Our approach exhibits promise in the noisy intermediate-scale quantum environment by providing a rapid and optimal method for synthesizing multi-bit Toffoli gates in diverse and unpredictable quantum hardware specifications.
Quantum circuits currently constitute a dominant model for quantum computation [14]. Our work addresses the problem of constructing quantum circuits to implement an arbitrary given quantum computation, in the special case of two qubits. We pursue circuits without ancilla qubits and as small a number of elementary quantum gates [1, 9] as possible. Our lower bound for worst-case optimal two-qubit circuits calls for at least 17 gates: 15 one-qubit rotations and 2 CNOTs. To this end, we constructively prove a worstcase upper bound of 23 elementary gates, of which at most 4 (CNOTs) entail multi-qubit interactions. Our analysis shows that previously known synthesis algorithms, although more general, entail much larger quantum circuits than ours in the special case of two qubits. One such algorithm [4] has a worst case of 61 gates of which 18 may be CNOTs. Our techniques rely on the KAK decomposition from Lie theory as well as the polar and spectral (symmetric Shur) matrix decompositions from numerical analysis. They are related to the canonical decomposition of a two-qubit gate with respect to the "magic basis" of phase-shifted Bell states [11, 12]. We extend this decomposition in terms of elementary gates for quantum computation.