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Results in Physics

Two-qubit entangling gates for superconducting quantum computers

M. AbuGhanem, Hichem Eleuch

Published Dec 3, 2023• 19 citations
Publisher

Abstract

Noisy intermediate-scale quantum computers (NISQ) have demonstrated superior performance compared to conventional computing schemes. Nonetheless, errors associated with two-qubit entangling gates remain a substantial obstacle in fully harnessing the potential of current superconducting quantum computers. The achievement of quantum computation and quantum information processing critically depends on the presence of entangled states. These states are indispensable for quantum computers to surpass classical computers in terms of computational power. This paper presents a comprehensive characterization of a two-qubit entangling gate, known as Dagwood Bumstead (DB) gate, to investigate the challenges posed by errors in the DB gate on NISQ devices. Firstly, we propose a scheme for the realization of the DB gate using two capacitively coupled Josephson Superconducting qubits, based on the experimental setup carried out in Bialczak et al. (2010). The gate’s performance is fully described through quantum process tomography (QPT) and quantum state tomography (QST) experiments conducted in three different environments: noisy, noiseless, and on a real IBM quantum computer. The process fidelity of the DB gate is measured to be 0.8069705, and the state fidelity is determined to be 0.8858750. This study offers valuable insights into the performance of the DB gate on a NISQ device, showcasing its potential for executing intricate algorithms and operations on an authentic quantum computer.

DOI
10.1016/j.rinp.2023.107236

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Noisy intermediate-scale quantum computers (NISQ) have demonstrated superior performance compared to conventional computing schemes. Nonetheless, errors associated with two-qubit entangling gates remain a substantial obstacle in fully harnessing the potential of current superconducting quantum computers. The achievement of quantum computation and quantum information processing critically depends on the presence of entangled states. These states are indispensable for quantum computers to surpass classical computers in terms of computational power. This paper presents a comprehensive characterization of a two-qubit entangling gate, known as Dagwood Bumstead (DB) gate, to investigate the challenges posed by errors in the DB gate on NISQ devices. Firstly, we propose a scheme for the realization of the DB gate using two capacitively coupled Josephson Superconducting qubits, based on the experimental setup carried out in Bialczak et al. (2010). The gate’s performance is fully described through quantum process tomography (QPT) and quantum state tomography (QST) experiments conducted in three different environments: noisy, noiseless, and on a real IBM quantum computer. The process fidelity of the DB gate is measured to be 0.8069705, and the state fidelity is determined to be 0.8858750. This study offers valuable insights into the performance of the DB gate on a NISQ device, showcasing its potential for executing intricate algorithms and operations on an authentic quantum computer.
The Berkeley gate is a high-performance, two-qubit entangling operation with particular potential for quantum error correction and fault-tolerant protocols. However, harnessing this potential on current noisy intermediate-scale quantum (NISQ) processors, requires efficient compilation and robust performance under realistic noise conditions. In this work, we demonstrate a hardware-efficient implementation of the Berkeley gate on a superconducting quantum processor. Using quantum process tomography (QPT), we experimentally characterize its performance and benchmark it against a noiseless quantum simulator to evaluate its practical reliability in the NISQ era. Experimental measurements confirm the gate's correct logical action, producing the target partially entangled state with a subspace confinement probability of [Formula: see text] on real quantum hardware compared to 100% in quantum simulation. Results from QPT experiments show a simulated process fidelity of [Formula: see text], while the experimental process fidelity on hardware is [Formula: see text]. The observed discrepancy is analyzed in the context of device-specific noise sources, including qubit relaxation, dephasing, and state preparation and measurement (SPAM) errors. Our work provides a concrete fidelity benchmark for the Berkeley gate on superconducting hardware and quantify the impact of realistic noise on a non-trivial two-qubit operation, supporting its use in near-term algorithmic and error-correction applications.
Abstract A single-shot entangling gate plays a crucial role in quantum information processing due to its high fidelity. This operation gate is fast to create a maximally entangled state and forms a universal gate set for quantum computing. Currently, the preparation and demonstration of multi-qubit entanglement are achieved based on sequences of single- and two-qubit operations, yielding lower fidelity and requiring longer execution time. Here, we demonstrate by numerically simulating the use of quantum process tomography to fully characterize the performance of a single-shot three-qubit entangling gate. This gate is used to create a Greenberger–Horne–Zeilinger entangled state in Sakhouf et al (2021 J. Phys. B: At. Mol. Opt. Phys. 54 175501), directly generated by three transmon-type superconducting qubits which are mediated by a resonator with the assistance of a microwave field. Comparing ideal and simulated quantum process tomography, we characterize the entangling gate performance by calculating the mean fidelity achieving a high value ≻ 0.93 .
Abstract The Mølmer–Sørensen gate, a cornerstone entangling operation in trapped-ion systems, represents a promising alternative to standard entangling gates in superconducting quantum architectures. However, its performance on superconducting hardware has remained unverified. In this work, we present a hardware-efficient implementation of the Mølmer–Sørensen gate and characterize its performance using quantum process tomography (QPT) on IBM Quantum’s superconducting processors. Our implementation achieves a process fidelity of 92.47% on the real quantum hardware, a performance competitive with the 93.02% fidelity of the device’s native controlled-NOT (CX) gate. Furthermore, for the ∣00⟩\vert {00} \rangle ∣00⟩ | 00 ⟩ input state, the gate prepares the target Bell state with 94.2%94.2\%94.2% 94.2 % success probability, confirming its correct logical operation. These results demonstrate that non-native entangling gates can be optimized to perform on par with hardware-native operations. This work expands the effective gate set for algorithm design on fixed-architecture processors and provides a critical benchmark for cross-platform gate evaluation, underscoring the role of hardware-aware compilation in advancing noisy intermediate-scale quantum (NISQ) computing.
While the common practice of decomposing general quantum algorithms into a collection of single- and two-qubit gates is conceptually simple, in many cases it is possible to have more efficient solutions where quantum gates engaging multiple qubits are used. In the noisy intermediate-scale quantum (NISQ) era where a universal error correction is still unavailable, this strategy is particularly appealing since it can significantly reduce the computational resources required for executing quantum algorithms. In this work, we experimentally investigate a three-qubit Controlled-CPHASE-SWAP (CCZS) gate on superconducting quantum circuits. By exploiting the higher energy levels of superconducting qubits, we are able to realize a Fredkin-like CCZS gate with a duration of 40 ns, which is comparable to typical single- and two-qubit gates realized on the same platform. By performing quantum process tomography for the two target qubits, we obtain a process fidelity of 86.0% and 81.1% for the control qubit being prepared in ∣0〉 and ∣1〉, respectively. We also show that our scheme can be readily extended to realize a general CCZS gate with an arbitrary swap angle. The results reported here provide valuable additions to the toolbox for achieving large-scale hardware-efficient quantum circuits.
Abstract Characterizing quantum dynamics is critical in quantum physics, quantum information science, and computation, where the precision of quantum gates plays a key role. We present a comprehensive experimental analysis of the SQSCZ gate–a novel universal two-qubit entangling gate combining SWAP\sqrt{\text {SWAP}}SWAP​ SWAP and CZ\sqrt{\text {CZ}}CZ​ CZ operations–on superconducting quantum hardware. Leveraging quantum process tomography via the Choi-Jamiołkowski isomorphism, we benchmark the gate’s performance across different noise environments. Experimental results demonstrate high process fidelities of 97.27%97.27\%97.27% 97.27 % (quantum simulator) and 88.99%88.99\%88.99% 88.99 % (quantum hardware), revealing remarkable noise resilience. Owing to its hybrid architecture, circuit depth reduction capabilities, and hardware-efficient decomposition into only two CNOT gates, the SQSCZ gate holds strong potential for near-term quantum applications, including the Quantum Fourier Transform and Variational Quantum Eigensolvers for molecular simulations. These findings establish the SQSCZ gate as a promising primitive for NISQ-era quantum algorithms, while providing key insights into gate-level error processes in superconducting quantum processors.
Quantum devices in the noisy intermediate-scale quantum (NISQ) era are highly susceptible to different types of quantum noise, which directly impact the reliability of experimental results. This work provides a characterization of error behavior arising from quantum noises on IBM's superconducting quantum processor, offering practical insights for algorithm design, benchmarking, and error-mitigation strategies on a real superconducting quantum processor in the NISQ era. The study begins with the measurement of the basis state, without applying any gate, to quantify state-preparation and measurement (SPAM) errors. Additionally, the errors are further quantified due to the application of single-qubit Pauli-X, two-qubit CNOT gate and other multi-qubit Controlled-X gates. Each circuit was executed with 1024 shots, and the percentage error between the expected and observed outputs was computed. The results show that the single-qubit Pauli-X gate exhibits relatively low errors in comparison with the two-qubit CNOT gate, whereas other multi-qubit Controlled-X gates lead to significantly higher deviations. This work also analyzes the noise effect of a fourqubit Controlled-X gate being implemented using a three-qubit Controlled-X gate with an extra auxiliary qubit, and the result shows a significant reduction in the error rate.