Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

arXiv:2510.07352 · Quantum Information Processing

A hardware-efficient Mølmer–Sørensen gate for superconducting quantum computers

M. AbuGhanem

Published Apr 21, 2026• 1 citation
arXivHTMLPDF

Abstract

Abstract The Mølmer–Sørensen gate, a cornerstone entangling operation in trapped-ion systems, represents a promising alternative to standard entangling gates in superconducting quantum architectures. However, its performance on superconducting hardware has remained unverified. In this work, we present a hardware-efficient implementation of the Mølmer–Sørensen gate and characterize its performance using quantum process tomography (QPT) on IBM Quantum’s superconducting processors. Our implementation achieves a process fidelity of 92.47% on the real quantum hardware, a performance competitive with the 93.02% fidelity of the device’s native controlled-NOT (CX) gate. Furthermore, for the $$\vert {00} \rangle $$ | 00 ⟩ input state, the gate prepares the target Bell state with $$94.2\%$$ 94.2 % success probability, confirming its correct logical operation. These results demonstrate that non-native entangling gates can be optimized to perform on par with hardware-native operations. This work expands the effective gate set for algorithm design on fixed-architecture processors and provides a critical benchmark for cross-platform gate evaluation, underscoring the role of hardware-aware compilation in advancing noisy intermediate-scale quantum (NISQ) computing.

DOI
10.1007/s11128-026-05167-4

Related papers

A hardware-efficient Berkeley gate for superconducting quantum processors

M. AbuGhanem

The Berkeley gate is a high-performance, two-qubit entangling operation with particular potential for quantum error correction and fault-tolerant protocols. However, harnessing this potential on current noisy intermediate-scale quantum (NISQ) processors, requires efficient compilation and robust performance under realistic noise conditions. In this work, we demonstrate a hardware-efficient implementation of the Berkeley gate on a superconducting quantum processor. Using quantum process tomography (QPT), we experimentally characterize its performance and benchmark it against a noiseless quantum simulator to evaluate its practical reliability in the NISQ era. Experimental measurements confirm the gate's correct logical action, producing the target partially entangled state with a subspace confinement probability of [Formula: see text] on real quantum hardware compared to 100% in quantum simulation. Results from QPT experiments show a simulated process fidelity of [Formula: see text], while the experimental process fidelity on hardware is [Formula: see text]. The observed discrepancy is analyzed in the context of device-specific noise sources, including qubit relaxation, dephasing, and state preparation and measurement (SPAM) errors. Our work provides a concrete fidelity benchmark for the Berkeley gate on superconducting hardware and quantify the impact of realistic noise on a non-trivial two-qubit operation, supporting its use in near-term algorithmic and error-correction applications.

Scientific Reports•Jun 5, 2026•0 citations

Characterizing conditional quantum dynamics on superconducting quantum processors

M. AbuGhanem

Abstract The pursuit of practical quantum computation relies on the precise implementation and characterization of high-fidelity entangling gates. We present a detailed experimental characterization of the controlled-NOT (CX) and controlled-phase (CZ) gates on a noisy intermediate-scale quantum (NISQ) superconducting processor using full quantum process tomography and direct state measurements. The gates were benchmarked against a noise-free quantum simulator to isolate hardware-induced errors. The CX gate, implemented as a native gate, achieved an average process fidelity of $$\mathcal {F}_p^{\text {CX}} = 93.02\%$$ F p CX = 93.02 % and correctly prepared the target state with $$P_{00}^{\text {CX}} = 92.40\%$$ P 00 CX = 92.40 % probability. The CZ gate, decomposed into a sequence of single-qubit and CX gates, achieved $$\mathcal {F}_p^{\text {CZ}} = 92.59\%$$ F p CZ = 92.59 % with superior state-preparation fidelity of $$P_{00}^{\text {CZ}} = 97.08\%$$ P 00 CZ = 97.08 % . Remarkably, the compiled CZ gate outperformed the native CX gate in state preservation by 4.68-percentage points, demonstrating the effectiveness of hardware-aware compilation. Our analysis provides a comprehensive benchmark of these essential gates, revealing that compilation strategy can be as crucial as native hardware performance for reliable quantum circuit execution in the NISQ era.

The European Physical Journal Plus•Feb 9, 2026•2 citations

Benchmarking engineered exchange interactions on NISQ hardware

M. AbuGhanem

Engineered exchange interactions, realized through the iSWAP and [Formula: see text] gates, play a fundamental role in entangling operations for quantum algorithms, simulation of spin-exchange dynamics, and optimized qubit connectivity. In this work, we present hardware-aware implementations of the iSWAP and [Formula: see text] gates tailored to superconducting quantum processors, along with comprehensive characterization using both quantum process tomography (QPT) and direct state measurements (DSM). QPT results show process fidelities of 97.32% (iSWAP) and 98.02% ([Formula: see text]) on quantum simulator, decreasing to 89.72% and 87.65% on quantum hardware, respectively. DSM on the [Formula: see text] input state reveals that the iSWAP implementation achieves higher state preservation fidelity on hardware (93.53% vs. 92.44% for [Formula: see text]) but shows higher measured [Formula: see text] population (2.26% vs. 0.38%). These results establish a benchmark for anisotropic exchange gates on noisy intermediate-scale quantum (NISQ) hardware and provide quantitative performance data to inform gate selection for quantum circuit design in the NISQ era.

Scientific Reports•May 25, 2026•0 citations

Hardware-Conscious Optimization of the Quantum Toffoli Gate

Max Aksel Bowman, Pranav Gokhale, Jeffrey M. Larson +2 more

While quantum computing holds great potential in combinatorial optimization, electronic structure calculation, and number theory, the current era of quantum computing is limited by noisy hardware. Many quantum compilation approaches can mitigate the effects of imperfect hardware by optimizing quantum circuits for objectives such as critical path length. Few approaches consider quantum circuits in terms of the set of vendor-calibrated operations (i.e., native gates) available on target hardware. This manuscript expands the analytical and numerical approaches for optimizing quantum circuits at this abstraction level. We present a procedure for combining the strengths of analytical native gate-level optimization with numerical optimization. Although we focus on optimizing Toffoli gates on the IBMQ native gate set, the methods presented are generalizable to any gate and superconducting qubit architecture. Our optimized Toffoli gate implementation demonstrates an 18% reduction in infidelity compared with the canonical implementation as benchmarked on IBM Jakarta with quantum process tomography. Assuming the inclusion of multi-qubit cross-resonance (MCR) gates in the IBMQ native gate set, we produce Toffoli implementations with only six multi-qubit gates, a 25% reduction from the canonical eight multi-qubit implementations for linearly connected qubits.

arXiv:2209.02669•ACM Transactions on Quantum Computing•Jul 20, 2023•13 citations

Investigation of Hardware Architecture Effects on Quantum Algorithm Performance: A Comparative Hardware Study

Askar Oralkhan, Temirlan Zhaxalykov

Cloud-accessible quantum processors enable direct execution of quantum algorithms on heterogeneous hardware platforms. Unlike classical systems, however, identical quantum circuits may exhibit substantially different behavior across devices due to architectural variations in qubit connectivity, gate fidelity, and coherence times. In this work, we systematically benchmark five representative quantum algorithms - Bell state preparation, GHZ state generation, Quantum Fourier Transform (QFT), Grover's Search, and the Quantum Approximate Optimization Algorithm (QAOA) - across trapped-ion, superconducting, and simulator backends using Amazon Braket. Performance metrics including fidelity, CHSH violation, success probability, circuit depth, and gate counts are evaluated. Our results demonstrate a strong dependence of algorithmic performance on hardware topology and noise characteristics. For example, 10-qubit GHZ states achieved fidelities above 0.8 on trapped-ion hardware, while superconducting platforms dropped below 0.15 due to routing overhead and accumulated two-qubit gate errors. These findings highlight the importance of hardware-aware algorithm selection and provide practical guidance for benchmarking in the NISQ era.

quant-pharXiv:2601.05286•Jan 8, 2026•0 citations

Full Quantum Process Tomography of a Universal Entangling Gate on an IBM’s Quantum Computer

M. AbuGhanem

Abstract Characterizing quantum dynamics is critical in quantum physics, quantum information science, and computation, where the precision of quantum gates plays a key role. We present a comprehensive experimental analysis of the SQSCZ gate–a novel universal two-qubit entangling gate combining $$\sqrt{\text {SWAP}}$$ SWAP and $$\sqrt{\text {CZ}}$$ CZ operations–on superconducting quantum hardware. Leveraging quantum process tomography via the Choi-Jamiołkowski isomorphism, we benchmark the gate’s performance across different noise environments. Experimental results demonstrate high process fidelities of $$97.27\%$$ 97.27 % (quantum simulator) and $$88.99\%$$ 88.99 % (quantum hardware), revealing remarkable noise resilience. Owing to its hybrid architecture, circuit depth reduction capabilities, and hardware-efficient decomposition into only two CNOT gates, the SQSCZ gate holds strong potential for near-term quantum applications, including the Quantum Fourier Transform and Variational Quantum Eigensolvers for molecular simulations. These findings establish the SQSCZ gate as a promising primitive for NISQ-era quantum algorithms, while providing key insights into gate-level error processes in superconducting quantum processors.

arXiv:2402.06946•Arabian Journal for Science and Engineering•Jul 4, 2025•9 citations
Abstract The Mølmer–Sørensen gate, a cornerstone entangling operation in trapped-ion systems, represents a promising alternative to standard entangling gates in superconducting quantum architectures. However, its performance on superconducting hardware has remained unverified. In this work, we present a hardware-efficient implementation of the Mølmer–Sørensen gate and characterize its performance using quantum process tomography (QPT) on IBM Quantum’s superconducting processors. Our implementation achieves a process fidelity of 92.47% on the real quantum hardware, a performance competitive with the 93.02% fidelity of the device’s native controlled-NOT (CX) gate. Furthermore, for the ∣00⟩\vert {00} \rangle ∣00⟩ | 00 ⟩ input state, the gate prepares the target Bell state with 94.2%94.2\%94.2% 94.2 % success probability, confirming its correct logical operation. These results demonstrate that non-native entangling gates can be optimized to perform on par with hardware-native operations. This work expands the effective gate set for algorithm design on fixed-architecture processors and provides a critical benchmark for cross-platform gate evaluation, underscoring the role of hardware-aware compilation in advancing noisy intermediate-scale quantum (NISQ) computing.
The Berkeley gate is a high-performance, two-qubit entangling operation with particular potential for quantum error correction and fault-tolerant protocols. However, harnessing this potential on current noisy intermediate-scale quantum (NISQ) processors, requires efficient compilation and robust performance under realistic noise conditions. In this work, we demonstrate a hardware-efficient implementation of the Berkeley gate on a superconducting quantum processor. Using quantum process tomography (QPT), we experimentally characterize its performance and benchmark it against a noiseless quantum simulator to evaluate its practical reliability in the NISQ era. Experimental measurements confirm the gate's correct logical action, producing the target partially entangled state with a subspace confinement probability of [Formula: see text] on real quantum hardware compared to 100% in quantum simulation. Results from QPT experiments show a simulated process fidelity of [Formula: see text], while the experimental process fidelity on hardware is [Formula: see text]. The observed discrepancy is analyzed in the context of device-specific noise sources, including qubit relaxation, dephasing, and state preparation and measurement (SPAM) errors. Our work provides a concrete fidelity benchmark for the Berkeley gate on superconducting hardware and quantify the impact of realistic noise on a non-trivial two-qubit operation, supporting its use in near-term algorithmic and error-correction applications.
Abstract The pursuit of practical quantum computation relies on the precise implementation and characterization of high-fidelity entangling gates. We present a detailed experimental characterization of the controlled-NOT (CX) and controlled-phase (CZ) gates on a noisy intermediate-scale quantum (NISQ) superconducting processor using full quantum process tomography and direct state measurements. The gates were benchmarked against a noise-free quantum simulator to isolate hardware-induced errors. The CX gate, implemented as a native gate, achieved an average process fidelity of FpCX=93.02%\mathcal {F}_p^{\text {CX}} = 93.02\%FpCX​=93.02% F p CX = 93.02 % and correctly prepared the target state with P00CX=92.40%P_{00}^{\text {CX}} = 92.40\%P00CX​=92.40% P 00 CX = 92.40 % probability. The CZ gate, decomposed into a sequence of single-qubit and CX gates, achieved FpCZ=92.59%\mathcal {F}_p^{\text {CZ}} = 92.59\%FpCZ​=92.59% F p CZ = 92.59 % with superior state-preparation fidelity of P00CZ=97.08%P_{00}^{\text {CZ}} = 97.08\%P00CZ​=97.08% P 00 CZ = 97.08 % . Remarkably, the compiled CZ gate outperformed the native CX gate in state preservation by 4.68-percentage points, demonstrating the effectiveness of hardware-aware compilation. Our analysis provides a comprehensive benchmark of these essential gates, revealing that compilation strategy can be as crucial as native hardware performance for reliable quantum circuit execution in the NISQ era.
Engineered exchange interactions, realized through the iSWAP and [Formula: see text] gates, play a fundamental role in entangling operations for quantum algorithms, simulation of spin-exchange dynamics, and optimized qubit connectivity. In this work, we present hardware-aware implementations of the iSWAP and [Formula: see text] gates tailored to superconducting quantum processors, along with comprehensive characterization using both quantum process tomography (QPT) and direct state measurements (DSM). QPT results show process fidelities of 97.32% (iSWAP) and 98.02% ([Formula: see text]) on quantum simulator, decreasing to 89.72% and 87.65% on quantum hardware, respectively. DSM on the [Formula: see text] input state reveals that the iSWAP implementation achieves higher state preservation fidelity on hardware (93.53% vs. 92.44% for [Formula: see text]) but shows higher measured [Formula: see text] population (2.26% vs. 0.38%). These results establish a benchmark for anisotropic exchange gates on noisy intermediate-scale quantum (NISQ) hardware and provide quantitative performance data to inform gate selection for quantum circuit design in the NISQ era.
While quantum computing holds great potential in combinatorial optimization, electronic structure calculation, and number theory, the current era of quantum computing is limited by noisy hardware. Many quantum compilation approaches can mitigate the effects of imperfect hardware by optimizing quantum circuits for objectives such as critical path length. Few approaches consider quantum circuits in terms of the set of vendor-calibrated operations (i.e., native gates) available on target hardware. This manuscript expands the analytical and numerical approaches for optimizing quantum circuits at this abstraction level. We present a procedure for combining the strengths of analytical native gate-level optimization with numerical optimization. Although we focus on optimizing Toffoli gates on the IBMQ native gate set, the methods presented are generalizable to any gate and superconducting qubit architecture. Our optimized Toffoli gate implementation demonstrates an 18% reduction in infidelity compared with the canonical implementation as benchmarked on IBM Jakarta with quantum process tomography. Assuming the inclusion of multi-qubit cross-resonance (MCR) gates in the IBMQ native gate set, we produce Toffoli implementations with only six multi-qubit gates, a 25% reduction from the canonical eight multi-qubit implementations for linearly connected qubits.
Cloud-accessible quantum processors enable direct execution of quantum algorithms on heterogeneous hardware platforms. Unlike classical systems, however, identical quantum circuits may exhibit substantially different behavior across devices due to architectural variations in qubit connectivity, gate fidelity, and coherence times. In this work, we systematically benchmark five representative quantum algorithms - Bell state preparation, GHZ state generation, Quantum Fourier Transform (QFT), Grover's Search, and the Quantum Approximate Optimization Algorithm (QAOA) - across trapped-ion, superconducting, and simulator backends using Amazon Braket. Performance metrics including fidelity, CHSH violation, success probability, circuit depth, and gate counts are evaluated. Our results demonstrate a strong dependence of algorithmic performance on hardware topology and noise characteristics. For example, 10-qubit GHZ states achieved fidelities above 0.8 on trapped-ion hardware, while superconducting platforms dropped below 0.15 due to routing overhead and accumulated two-qubit gate errors. These findings highlight the importance of hardware-aware algorithm selection and provide practical guidance for benchmarking in the NISQ era.
Abstract Characterizing quantum dynamics is critical in quantum physics, quantum information science, and computation, where the precision of quantum gates plays a key role. We present a comprehensive experimental analysis of the SQSCZ gate–a novel universal two-qubit entangling gate combining SWAP\sqrt{\text {SWAP}}SWAP​ SWAP and CZ\sqrt{\text {CZ}}CZ​ CZ operations–on superconducting quantum hardware. Leveraging quantum process tomography via the Choi-Jamiołkowski isomorphism, we benchmark the gate’s performance across different noise environments. Experimental results demonstrate high process fidelities of 97.27%97.27\%97.27% 97.27 % (quantum simulator) and 88.99%88.99\%88.99% 88.99 % (quantum hardware), revealing remarkable noise resilience. Owing to its hybrid architecture, circuit depth reduction capabilities, and hardware-efficient decomposition into only two CNOT gates, the SQSCZ gate holds strong potential for near-term quantum applications, including the Quantum Fourier Transform and Variational Quantum Eigensolvers for molecular simulations. These findings establish the SQSCZ gate as a promising primitive for NISQ-era quantum algorithms, while providing key insights into gate-level error processes in superconducting quantum processors.