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Scientific Reports

A hardware-efficient Berkeley gate for superconducting quantum processors

M. AbuGhanem

Published Jun 5, 2026• 0 citations
Publisher

Abstract

The Berkeley gate is a high-performance, two-qubit entangling operation with particular potential for quantum error correction and fault-tolerant protocols. However, harnessing this potential on current noisy intermediate-scale quantum (NISQ) processors, requires efficient compilation and robust performance under realistic noise conditions. In this work, we demonstrate a hardware-efficient implementation of the Berkeley gate on a superconducting quantum processor. Using quantum process tomography (QPT), we experimentally characterize its performance and benchmark it against a noiseless quantum simulator to evaluate its practical reliability in the NISQ era. Experimental measurements confirm the gate's correct logical action, producing the target partially entangled state with a subspace confinement probability of [Formula: see text] on real quantum hardware compared to 100% in quantum simulation. Results from QPT experiments show a simulated process fidelity of [Formula: see text], while the experimental process fidelity on hardware is [Formula: see text]. The observed discrepancy is analyzed in the context of device-specific noise sources, including qubit relaxation, dephasing, and state preparation and measurement (SPAM) errors. Our work provides a concrete fidelity benchmark for the Berkeley gate on superconducting hardware and quantify the impact of realistic noise on a non-trivial two-qubit operation, supporting its use in near-term algorithmic and error-correction applications.

DOI
10.1038/s41598-026-56236-8

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The Berkeley gate is a high-performance, two-qubit entangling operation with particular potential for quantum error correction and fault-tolerant protocols. However, harnessing this potential on current noisy intermediate-scale quantum (NISQ) processors, requires efficient compilation and robust performance under realistic noise conditions. In this work, we demonstrate a hardware-efficient implementation of the Berkeley gate on a superconducting quantum processor. Using quantum process tomography (QPT), we experimentally characterize its performance and benchmark it against a noiseless quantum simulator to evaluate its practical reliability in the NISQ era. Experimental measurements confirm the gate's correct logical action, producing the target partially entangled state with a subspace confinement probability of [Formula: see text] on real quantum hardware compared to 100% in quantum simulation. Results from QPT experiments show a simulated process fidelity of [Formula: see text], while the experimental process fidelity on hardware is [Formula: see text]. The observed discrepancy is analyzed in the context of device-specific noise sources, including qubit relaxation, dephasing, and state preparation and measurement (SPAM) errors. Our work provides a concrete fidelity benchmark for the Berkeley gate on superconducting hardware and quantify the impact of realistic noise on a non-trivial two-qubit operation, supporting its use in near-term algorithmic and error-correction applications.
Abstract The Mølmer–Sørensen gate, a cornerstone entangling operation in trapped-ion systems, represents a promising alternative to standard entangling gates in superconducting quantum architectures. However, its performance on superconducting hardware has remained unverified. In this work, we present a hardware-efficient implementation of the Mølmer–Sørensen gate and characterize its performance using quantum process tomography (QPT) on IBM Quantum’s superconducting processors. Our implementation achieves a process fidelity of 92.47% on the real quantum hardware, a performance competitive with the 93.02% fidelity of the device’s native controlled-NOT (CX) gate. Furthermore, for the ∣00⟩\vert {00} \rangle ∣00⟩ | 00 ⟩ input state, the gate prepares the target Bell state with 94.2%94.2\%94.2% 94.2 % success probability, confirming its correct logical operation. These results demonstrate that non-native entangling gates can be optimized to perform on par with hardware-native operations. This work expands the effective gate set for algorithm design on fixed-architecture processors and provides a critical benchmark for cross-platform gate evaluation, underscoring the role of hardware-aware compilation in advancing noisy intermediate-scale quantum (NISQ) computing.
Abstract The pursuit of practical quantum computation relies on the precise implementation and characterization of high-fidelity entangling gates. We present a detailed experimental characterization of the controlled-NOT (CX) and controlled-phase (CZ) gates on a noisy intermediate-scale quantum (NISQ) superconducting processor using full quantum process tomography and direct state measurements. The gates were benchmarked against a noise-free quantum simulator to isolate hardware-induced errors. The CX gate, implemented as a native gate, achieved an average process fidelity of FpCX=93.02%\mathcal {F}_p^{\text {CX}} = 93.02\%FpCX​=93.02% F p CX = 93.02 % and correctly prepared the target state with P00CX=92.40%P_{00}^{\text {CX}} = 92.40\%P00CX​=92.40% P 00 CX = 92.40 % probability. The CZ gate, decomposed into a sequence of single-qubit and CX gates, achieved FpCZ=92.59%\mathcal {F}_p^{\text {CZ}} = 92.59\%FpCZ​=92.59% F p CZ = 92.59 % with superior state-preparation fidelity of P00CZ=97.08%P_{00}^{\text {CZ}} = 97.08\%P00CZ​=97.08% P 00 CZ = 97.08 % . Remarkably, the compiled CZ gate outperformed the native CX gate in state preservation by 4.68-percentage points, demonstrating the effectiveness of hardware-aware compilation. Our analysis provides a comprehensive benchmark of these essential gates, revealing that compilation strategy can be as crucial as native hardware performance for reliable quantum circuit execution in the NISQ era.
Noisy intermediate-scale quantum computers (NISQ) have demonstrated superior performance compared to conventional computing schemes. Nonetheless, errors associated with two-qubit entangling gates remain a substantial obstacle in fully harnessing the potential of current superconducting quantum computers. The achievement of quantum computation and quantum information processing critically depends on the presence of entangled states. These states are indispensable for quantum computers to surpass classical computers in terms of computational power. This paper presents a comprehensive characterization of a two-qubit entangling gate, known as Dagwood Bumstead (DB) gate, to investigate the challenges posed by errors in the DB gate on NISQ devices. Firstly, we propose a scheme for the realization of the DB gate using two capacitively coupled Josephson Superconducting qubits, based on the experimental setup carried out in Bialczak et al. (2010). The gate’s performance is fully described through quantum process tomography (QPT) and quantum state tomography (QST) experiments conducted in three different environments: noisy, noiseless, and on a real IBM quantum computer. The process fidelity of the DB gate is measured to be 0.8069705, and the state fidelity is determined to be 0.8858750. This study offers valuable insights into the performance of the DB gate on a NISQ device, showcasing its potential for executing intricate algorithms and operations on an authentic quantum computer.
Quantum devices in the noisy intermediate-scale quantum (NISQ) era are highly susceptible to different types of quantum noise, which directly impact the reliability of experimental results. This work provides a characterization of error behavior arising from quantum noises on IBM's superconducting quantum processor, offering practical insights for algorithm design, benchmarking, and error-mitigation strategies on a real superconducting quantum processor in the NISQ era. The study begins with the measurement of the basis state, without applying any gate, to quantify state-preparation and measurement (SPAM) errors. Additionally, the errors are further quantified due to the application of single-qubit Pauli-X, two-qubit CNOT gate and other multi-qubit Controlled-X gates. Each circuit was executed with 1024 shots, and the percentage error between the expected and observed outputs was computed. The results show that the single-qubit Pauli-X gate exhibits relatively low errors in comparison with the two-qubit CNOT gate, whereas other multi-qubit Controlled-X gates lead to significantly higher deviations. This work also analyzes the noise effect of a fourqubit Controlled-X gate being implemented using a three-qubit Controlled-X gate with an extra auxiliary qubit, and the result shows a significant reduction in the error rate.
Engineered exchange interactions, realized through the iSWAP and [Formula: see text] gates, play a fundamental role in entangling operations for quantum algorithms, simulation of spin-exchange dynamics, and optimized qubit connectivity. In this work, we present hardware-aware implementations of the iSWAP and [Formula: see text] gates tailored to superconducting quantum processors, along with comprehensive characterization using both quantum process tomography (QPT) and direct state measurements (DSM). QPT results show process fidelities of 97.32% (iSWAP) and 98.02% ([Formula: see text]) on quantum simulator, decreasing to 89.72% and 87.65% on quantum hardware, respectively. DSM on the [Formula: see text] input state reveals that the iSWAP implementation achieves higher state preservation fidelity on hardware (93.53% vs. 92.44% for [Formula: see text]) but shows higher measured [Formula: see text] population (2.26% vs. 0.38%). These results establish a benchmark for anisotropic exchange gates on noisy intermediate-scale quantum (NISQ) hardware and provide quantitative performance data to inform gate selection for quantum circuit design in the NISQ era.
Abstract Characterizing quantum dynamics is critical in quantum physics, quantum information science, and computation, where the precision of quantum gates plays a key role. We present a comprehensive experimental analysis of the SQSCZ gate–a novel universal two-qubit entangling gate combining SWAP\sqrt{\text {SWAP}}SWAP​ SWAP and CZ\sqrt{\text {CZ}}CZ​ CZ operations–on superconducting quantum hardware. Leveraging quantum process tomography via the Choi-Jamiołkowski isomorphism, we benchmark the gate’s performance across different noise environments. Experimental results demonstrate high process fidelities of 97.27%97.27\%97.27% 97.27 % (quantum simulator) and 88.99%88.99\%88.99% 88.99 % (quantum hardware), revealing remarkable noise resilience. Owing to its hybrid architecture, circuit depth reduction capabilities, and hardware-efficient decomposition into only two CNOT gates, the SQSCZ gate holds strong potential for near-term quantum applications, including the Quantum Fourier Transform and Variational Quantum Eigensolvers for molecular simulations. These findings establish the SQSCZ gate as a promising primitive for NISQ-era quantum algorithms, while providing key insights into gate-level error processes in superconducting quantum processors.