Quantum devices in the noisy intermediate-scale quantum (NISQ) era are highly susceptible to different types of quantum noise, which directly impact the reliability of experimental results. This work provides a characterization of error behavior arising from quantum noises on IBM's superconducting quantum processor, offering practical insights for algorithm design, benchmarking, and error-mitigation strategies on a real superconducting quantum processor in the NISQ era. The study begins with the measurement of the basis state, without applying any gate, to quantify state-preparation and measurement (SPAM) errors. Additionally, the errors are further quantified due to the application of single-qubit Pauli-X, two-qubit CNOT gate and other multi-qubit Controlled-X gates. Each circuit was executed with 1024 shots, and the percentage error between the expected and observed outputs was computed. The results show that the single-qubit Pauli-X gate exhibits relatively low errors in comparison with the two-qubit CNOT gate, whereas other multi-qubit Controlled-X gates lead to significantly higher deviations. This work also analyzes the noise effect of a fourqubit Controlled-X gate being implemented using a three-qubit Controlled-X gate with an extra auxiliary qubit, and the result shows a significant reduction in the error rate.
Quantum devices in the noisy intermediate-scale quantum (NISQ) era are highly susceptible to different types of quantum noise, which directly impact the reliability of experimental results. This work provides a characterization of error behavior arising from quantum noises on IBM's superconducting quantum processor, offering practical insights for algorithm design, benchmarking, and error-mitigation strategies on a real superconducting quantum processor in the NISQ era. The study begins with the measurement of the basis state, without applying any gate, to quantify state-preparation and measurement (SPAM) errors. Additionally, the errors are further quantified due to the application of single-qubit Pauli-X, two-qubit CNOT gate and other multi-qubit Controlled-X gates. Each circuit was executed with 1024 shots, and the percentage error between the expected and observed outputs was computed. The results show that the single-qubit Pauli-X gate exhibits relatively low errors in comparison with the two-qubit CNOT gate, whereas other multi-qubit Controlled-X gates lead to significantly higher deviations. This work also analyzes the noise effect of a fourqubit Controlled-X gate being implemented using a three-qubit Controlled-X gate with an extra auxiliary qubit, and the result shows a significant reduction in the error rate.
The Berkeley gate is a high-performance, two-qubit entangling operation with particular potential for quantum error correction and fault-tolerant protocols. However, harnessing this potential on current noisy intermediate-scale quantum (NISQ) processors, requires efficient compilation and robust performance under realistic noise conditions. In this work, we demonstrate a hardware-efficient implementation of the Berkeley gate on a superconducting quantum processor. Using quantum process tomography (QPT), we experimentally characterize its performance and benchmark it against a noiseless quantum simulator to evaluate its practical reliability in the NISQ era. Experimental measurements confirm the gate's correct logical action, producing the target partially entangled state with a subspace confinement probability of [Formula: see text] on real quantum hardware compared to 100% in quantum simulation. Results from QPT experiments show a simulated process fidelity of [Formula: see text], while the experimental process fidelity on hardware is [Formula: see text]. The observed discrepancy is analyzed in the context of device-specific noise sources, including qubit relaxation, dephasing, and state preparation and measurement (SPAM) errors. Our work provides a concrete fidelity benchmark for the Berkeley gate on superconducting hardware and quantify the impact of realistic noise on a non-trivial two-qubit operation, supporting its use in near-term algorithmic and error-correction applications.
Abstract The pursuit of practical quantum computation relies on the precise implementation and characterization of high-fidelity entangling gates. We present a detailed experimental characterization of the controlled-NOT (CX) and controlled-phase (CZ) gates on a noisy intermediate-scale quantum (NISQ) superconducting processor using full quantum process tomography and direct state measurements. The gates were benchmarked against a noise-free quantum simulator to isolate hardware-induced errors. The CX gate, implemented as a native gate, achieved an average process fidelity of FpCX=93.02% F p CX = 93.02 % and correctly prepared the target state with P00CX=92.40% P 00 CX = 92.40 % probability. The CZ gate, decomposed into a sequence of single-qubit and CX gates, achieved FpCZ=92.59% F p CZ = 92.59 % with superior state-preparation fidelity of P00CZ=97.08% P 00 CZ = 97.08 % . Remarkably, the compiled CZ gate outperformed the native CX gate in state preservation by 4.68-percentage points, demonstrating the effectiveness of hardware-aware compilation. Our analysis provides a comprehensive benchmark of these essential gates, revealing that compilation strategy can be as crucial as native hardware performance for reliable quantum circuit execution in the NISQ era.
The successful implementation of algorithms on quantum processors relies on the accurate control of quantum bits (qubits) to perform logic gate operations. In this era of noisy intermediate-scale quantum (NISQ) computing, systematic miscalibrations, drift, and crosstalk in the control of qubits can lead to a coherent form of error that has no classical analog. Coherent errors severely limit the performance of quantum algorithms in an unpredictable manner, and mitigating their impact is necessary for realizing reliable quantum computations. Moreover, the average error rates measured by randomized benchmarking and related protocols are not sensitive to the full impact of coherent errors and therefore do not reliably predict the global performance of quantum algorithms, leaving us unprepared to validate the accuracy of future large-scale quantum computations. Randomized compiling is a protocol designed to overcome these performance limitations by converting coherent errors into stochastic noise, dramatically reducing unpredictable errors in quantum algorithms and enabling accurate predictions of algorithmic performance from error rates measured via cycle benchmarking. In this work, we demonstrate significant performance gains under randomized compiling for the four-qubit quantum Fourier transform algorithm and for random circuits of variable depth on a superconducting quantum processor. Additionally, we accurately predict algorithm performance using experimentally measured error rates. Our results demonstrate that randomized compiling can be utilized to leverage and predict the capabilities of modern-day noisy quantum processors, paving the way forward for scalable quantum computing.
We experimentally study error mitigation and finite-shot sampling on superconducting quantum hardware under a constrained execution budget. The study combines calibration-aware qubit selection, circuit-depth scaling, zero-noise extrapolation, dynamical decoupling, readout-error mitigation, and repeated-shot estimation on an IBM Quantum processor. Experiments are organized across ideal simulation, noise-model simulation, and physical-device execution to separate sampling uncertainty from device-induced error. We investigate how mitigation performance changes with circuit depth, effective noise scale, qubit connectivity, and measurement budget, and quantify accuracy using expectation-value error, mean-squared error, statistical uncertainty, and mitigation gain. A fixed hardware-execution budget is used to evaluate shot allocation strategies and repeated measurements without relying on unlimited sampling. The resulting analysis provides a hardware-aware characterization of when mitigation improves expectation-value estimation and when finite-shot fluctuations offset the benefit of additional mitigation overhead. The implementation uses contemporary Qiskit and IBM Quantum Runtime workflows and is designed to provide reproducible experimental evidence for error-mitigation studies on current quantum processors.
Current advancements in technology have focused the attention of the quantum computing community toward exploring the potential of near-term devices whose computing power surpasses that of classical computers in practical applications. An unresolved central question revolves around whether the inherent noise in these devices can be overcome or whether any potential quantum advantage would be limited. There is no doubt that crosstalk is one of the main sources of noise in noisy intermediate-scale quantum (NISQ) systems, and it poses a fundamental challenge to hardware designs. Crosstalk between parallel instructions can corrupt quantum states and cause incorrect program execution. In this study, we present a necessary analysis of the crosstalk error effect on NISQ devices. Our approach is extremely straightforward and practical to estimate the crosstalk error of various multi-qubit devices. In particular, we combine the randomized benchmarking (RB) and simultaneous randomized benchmarking (SRB) protocol to estimate the crosstalk error from the correlation controlled-NOT (CNOT) gate. We demonstrate this protocol experimentally on 5-, 7-, \& 16-qubit devices. Our results demonstrate the crosstalk error model of three different IBM quantum devices over the experimental week and compare the error variation against the machine, number of qubits, quantum volume, processor, and topology. We then confirm the improvement in the circuit fidelity on different benchmarks by up to 3.06x via inserting an instruction barrier, as compared with an IBM quantum noisy device which offers near-optimal crosstalk mitigation in practice. Finally, we discuss the current system limitation, its tradeoff on fidelity and depth, noise beyond the NISQ system, and mitigation opportunities to ensure that the quantum operation can perform its quantum magic undisturbed.
Current noisy quantum computers have multiple types of errors, which can occur in the state preparation, measurement/readout, and gate operation, as well as intrinsic decoherence and relaxation. Partly motivated by the booming of intermediate-scale quantum processors, measurement and gate errors have been recently extensively studied, and several methods of mitigating them have been proposed and formulated in software packages (e.g., in IBM Qiskit). Despite this, the state preparation error and the procedure to quantify it have not yet been standardized, as state preparation and measurement errors are usually considered not directly separable. Inspired by a recent work of Laflamme, Lin, and Mor \cite{laflamme2022algorithmic}, we propose a simple and resource-efficient approach to quantify separately the state preparation and readout error rates. With these two errors separately quantified, we also propose methods to mitigate them separately, especially mitigating state preparation errors with linear (with the number of qubits) complexity. As a result of the separate mitigation, we show that the fidelity of the outcome can be improved by an order of magnitude compared to the standard measurement error mitigation scheme. We also show that the quantification and mitigation scheme is resilient against gate noise and can be immediately applied to current noisy quantum computers. To demonstrate this, we present results from cloud experiments on IBM's superconducting quantum computers. The results indicate that the state preparation error rate is also an important metric for qubit metrology that can be efficiently obtained.