A quantum instruction set is where quantum hardware and software meet. We develop characterization and compilation techniques for non-Clifford gates to accurately evaluate its designs. Applying these techniques to our fluxonium processor, we show that replacing the iSWAP gate by its square root SQiSW leads to a significant performance boost at almost no cost. More precisely, on SQiSW we measure a gate fidelity of up to 99.72% and averaging at 99.31%, and realize Haar random two-qubit gates with an average fidelity of 96.38%. This is an average error reduction of 41% for the former and a 50% reduction for the latter compared to using iSWAP on the same processor.
A quantum instruction set is where quantum hardware and software meet. We develop characterization and compilation techniques for non-Clifford gates to accurately evaluate its designs. Applying these techniques to our fluxonium processor, we show that replacing the iSWAP gate by its square root SQiSW leads to a significant performance boost at almost no cost. More precisely, on SQiSW we measure a gate fidelity of up to 99.72% and averaging at 99.31%, and realize Haar random two-qubit gates with an average fidelity of 96.38%. This is an average error reduction of 41% for the former and a 50% reduction for the latter compared to using iSWAP on the same processor.
The primary objective of quantum circuit synthesis is to efficiently and accurately realize specific quantum algorithms or operations utilizing a predefined set of quantum gates, while also optimizing the circuit size. It holds a pivotal position in Noisy Intermediate-Scale Quantum (NISQ) computation. Historically, most synthesis efforts have predominantly utilized CNOT or CZ gates as the 2-qubit gates. However, the SQiSW gate, also known as the square root of iSWAP gate, has garnered considerable attention due to its outstanding experimental performance with low error rates and high efficiency in 2-qubit gate synthesis. In this paper, we investigate the potential of the SQiSW gate in various synthesis problems by utilizing only the SQiSW gate along with arbitrary single-qubit gates, while optimizing the overall circuit size. For exact synthesis, the upper bound of SQiSW gates to synthesize arbitrary 3-qubit and n -qubit gates are 24 and 139 192 4 n ( 1 + o ( 1 ) ) respectively, which relies on the properties of SQiSW gate in Lie theory and Quantum Shannon Decomposition. We also introduce an exact synthesis scheme for Toffoli gate using only 8 SQiSW gates, which is grounded in numerical observation. More generally, with respect to numerical approximations, we provide a theoretical analysis of a pruning algorithm to reduce the size of the searching space in numerical experiment to 1 12 + o ( 1 ) of previous size, helping us reach the result that 11 SQiSW gates are enough in arbitrary 3-qubit gates synthesis up to an acceptable numerical error.
The quantum instruction set (QIS) is defined as the quantum gates that are physically realizable by controlling the qubits in quantum hardware. Compiling quantum circuits into the product of the gates in a properly defined QIS is a fundamental step in quantum computing. We here propose the quantum variational instruction set (QuVIS) formed by flexibly designed multiqubit gates for higher speed and accuracy of quantum computing. The controlling of qubits for realizing the gates in a QuVIS is variationally achieved using the fine-grained time optimization algorithm. Significant reductions in both the error accumulation and time cost are demonstrated in realizing the swaps of multiple qubits and quantum Fourier transformations, compared with the compiling by a standard QIS such as the quantum microinstruction set (QuMIS, formed by several one- and two-qubit gates including one-qubit rotations and controlled-not gates). With the same requirement on quantum hardware, the time cost for QuVIS is reduced to less than one-half of that for QuMIS. Simultaneously, the error is suppressed algebraically as the depth of the compiled circuit is reduced. As a general compiling approach with high flexibility and efficiency, QuVIS can be defined for different quantum circuits and be adapted to the quantum hardware with different interactions.
Most quantum compiling efforts rely on standard two-qubit basis gates, such as CX and iSWAP, to implement general quantum operations. However, with the advancement of quantum architecture design, more nonstandard two-qubit gates can now be implemented and calibrated on devices. Using these nonstandard gates may improve the performance of quantum computation. Despite this potential, it remains unclear how to efficiently incorporate these nonstandard gates into the quantum instruction set to enhance quantum advantage. To address this, we propose an analytical framework that facilitates the design of quantum instruction sets based on nonstandard gates. Our approach is grounded in the KAK decomposition and an analysis of the Cartan coordinate of two-qubit operations, enabling analytical conversion between any two two-qubit operations. This framework also demonstrates the lower and upper bounds of the conversion cost, revealing the relationship between the entangling power of two-qubit instructions and their Cartan coordinates. We further develop a compiler based on the analytical framework, which reduces the unitary decomposition cost with nonstandard two-qubit instructions. Using the proposed compiler, we evaluate various options for designing a quantum instruction set based on nonstandard gates. Our experiments demonstrate the efficiency of the proposed framework in the quantum instruction set design. Compared to the state-of-the-art method that is based on the numerical search, our framework reduces the time/resource overhead of exploring the instruction set design space by thousands of times. Moreover, with the established framework, we propose feasible designs for the quantum instruction set by modeling real-world quantum processors, further promoting the quantum advantage.
We propose SQiSW, the matrix square root of the standard iSWAP gate, as a native two-qubit gate for superconducting quantum computing. We show numerically that it has potential for an ultra-high fidelity implementation as its gate time is half of that of iSWAP, but at the same time it possesses powerful information processing capabilities in both the compilation of arbitrary two-qubit gates and the generation of large-scale entangled W-like states. Even though it is half of an iSWAP gate, its capabilities surprisingly rival and even surpass that of iSWAP or other incumbent native two-qubit gates such as CNOT. To complete the case for its candidacy, we propose a detailed compilation, calibration and benchmarking framework. In particular, we propose a variant of randomized benchmarking called interleaved fully randomized benchmarking (iFRB) which provides a general and unified solution for benchmarking non-Clifford gates such as SQiSW. For the reasons above, we believe that the SQiSW gate is worth further study and consideration as a native two-qubit gate for both fault-tolerant and noisy intermediate-scale quantum (NISQ) computation.
The design space of current quantum computers is expansive, with no obvious winning solution, leaving practitioners with a crucial question: “What is the optimal system configuration to run an algorithm?” This paper explores hardware design trade-offs across NISQ systems to better guide algorithm and hardware development. Algorithmic workloads and fidelity models drive the evaluation to appropriately capture architectural features such as gate expressivity, fidelity, and crosstalk. As a result of our analysis, we extend the criteria for gate design and selection from only maximizing average fidelity to a more comprehensive approach that additionally considers expressivity with respect to algorithm structures. A custom synthesis-driven compilation workflow that produces minimal circuit representations for a given system configuration drives our methodology and allows us to analyze any gate set effectively. In this work, we focus on native entangling gates (CNOT, ECR, CZ, ZZ, XX, Sycamore, √iSWAP), proposed gates (B Gate,4√CNOT, -8√CNOT), as well as parameterized gates (FSim, XY). By providing a method to evaluate the suitability of algorithms for hardware platforms, this work emphasizes the importance of hardware-software codesign for quantum computing.
Abstract It is advantageous for any quantum processor to support different classes of two-qubit quantum logic gates when compiling quantum circuits, a property that is typically not present in existing platforms. In particular, access to a gate set that includes support for the CZ-, iSWAP-, and SWAP-type families of gates renders conversions between these gate families unnecessary during compilation, as any two-qubit Clifford gate can be executed using at most one two-qubit gate from this set, plus additional single-qubit gates. We experimentally demonstrate that a SWAP gate can be decomposed into one iSWAP gate followed by one CZ gate, affirming a more efficient compilation strategy over the conventional approach that relies on three iSWAP or three CZ gates to replace a SWAP gate. Our implementation makes use of a superconducting quantum processor design based on fixed-frequency transmon qubits coupled together by a parametrically modulated tunable transmon coupler, extending this platform’s native gate set so that any two-qubit Clifford unitary matrix can be realized using no more than two two-qubit gates and single-qubit gates.