Most quantum compiling efforts rely on standard two-qubit basis gates, such as CX and iSWAP, to implement general quantum operations. However, with the advancement of quantum architecture design, more nonstandard two-qubit gates can now be implemented and calibrated on devices. Using these nonstandard gates may improve the performance of quantum computation. Despite this potential, it remains unclear how to efficiently incorporate these nonstandard gates into the quantum instruction set to enhance quantum advantage. To address this, we propose an analytical framework that facilitates the design of quantum instruction sets based on nonstandard gates. Our approach is grounded in the KAK decomposition and an analysis of the Cartan coordinate of two-qubit operations, enabling analytical conversion between any two two-qubit operations. This framework also demonstrates the lower and upper bounds of the conversion cost, revealing the relationship between the entangling power of two-qubit instructions and their Cartan coordinates. We further develop a compiler based on the analytical framework, which reduces the unitary decomposition cost with nonstandard two-qubit instructions. Using the proposed compiler, we evaluate various options for designing a quantum instruction set based on nonstandard gates. Our experiments demonstrate the efficiency of the proposed framework in the quantum instruction set design. Compared to the state-of-the-art method that is based on the numerical search, our framework reduces the time/resource overhead of exploring the instruction set design space by thousands of times. Moreover, with the established framework, we propose feasible designs for the quantum instruction set by modeling real-world quantum processors, further promoting the quantum advantage.
Most quantum compiling efforts rely on standard two-qubit basis gates, such as CX and iSWAP, to implement general quantum operations. However, with the advancement of quantum architecture design, more nonstandard two-qubit gates can now be implemented and calibrated on devices. Using these nonstandard gates may improve the performance of quantum computation. Despite this potential, it remains unclear how to efficiently incorporate these nonstandard gates into the quantum instruction set to enhance quantum advantage. To address this, we propose an analytical framework that facilitates the design of quantum instruction sets based on nonstandard gates. Our approach is grounded in the KAK decomposition and an analysis of the Cartan coordinate of two-qubit operations, enabling analytical conversion between any two two-qubit operations. This framework also demonstrates the lower and upper bounds of the conversion cost, revealing the relationship between the entangling power of two-qubit instructions and their Cartan coordinates. We further develop a compiler based on the analytical framework, which reduces the unitary decomposition cost with nonstandard two-qubit instructions. Using the proposed compiler, we evaluate various options for designing a quantum instruction set based on nonstandard gates. Our experiments demonstrate the efficiency of the proposed framework in the quantum instruction set design. Compared to the state-of-the-art method that is based on the numerical search, our framework reduces the time/resource overhead of exploring the instruction set design space by thousands of times. Moreover, with the established framework, we propose feasible designs for the quantum instruction set by modeling real-world quantum processors, further promoting the quantum advantage.
Near-term quantum computers are primarily limited by errors in quantum operations (or gates) between two quantum bits (or qubits). A physical machine typically provides a set of basis gates that include primitive 2-qubit (2Q) and 1-qubit (1Q) gates that can be implemented in a given technology. 2Q entangling gates, coupled with some 1Q gates, allow for universal quantum computation. In superconducting technologies, the current state of the art is to implement the same 2Q gate between every pair of qubits (typically an XX-or XY-type gate). This strict hardware uniformity requirement for 2Q gates in a large quantum computer has made scaling up a time and resource-intensive endeavor in the lab. We propose a radical idea – allow the 2Q basis gate(s) to differ between every pair of qubits, selecting the best entangling gates that can be calibrated between given pairs of qubits. This work aims to give quantum scientists the ability to run meaningful algorithms with qubit systems that are not perfectly uniform. Scientists will also be able to use a much broader variety of novel 2Q gates for quantum computing. We develop a theoretical framework for identifying good 2Q basis gates on “nonstandard” Cartan trajectories that deviate from “standard” trajectories like XX. We then introduce practical methods for calibration and compilation with nonstandard 2Q gates, and discuss possible ways to improve the compilation. To demonstrate our methods in a case study, we simulated both standard XY-type trajectories and faster, nonstandard trajectories using an entangling gate architecture with far-detuned transmon qubits. We identify efficient 2Q basis gates on these nonstandard trajectories and use them to compile a number of standard benchmark circuits such as QFT and QAOA. Our results demonstrate an 8x improvement over the baseline 2Q gates with respect to speed and coherence-limited gate fidelity.
A quantum instruction set is where quantum hardware and software meet. We develop characterization and compilation techniques for non-Clifford gates to accurately evaluate its designs. Applying these techniques to our fluxonium processor, we show that replacing the iSWAP gate by its square root SQiSW leads to a significant performance boost at almost no cost. More precisely, on SQiSW we measure a gate fidelity of up to 99.72% and averaging at 99.31%, and realize Haar random two-qubit gates with an average fidelity of 96.38%. This is an average error reduction of 41% for the former and a 50% reduction for the latter compared to using iSWAP on the same processor.
The design and architecture of a quantum instruction set are paramount to the performance of a quantum computer. This work introduces a gate scheme for qubits with XX + YY coupling that directly and efficiently realizes any two-qubit gate up to single-qubit gates. First, this scheme enables high-fidelity execution of quantum operations, especially when decoherence is the primary error source. Second, since the scheme spans the entire SU(4) group of two-qubit gates, we can use it to attain the optimal two-qubit gate count for algorithm implementation. These two advantages in synergy give rise to a quantum Complex yet Reduced Instruction Set Computer (CRISC). Though the gate scheme is compact, it supports a comprehensive array of quantum operations. This may seem paradoxical but is realizable due to the fundamental differences between quantum and classical computer architectures.
The existence of algorithm to machine gap has been accepted by the quantum computing domain experts, as the research community is struggling to realize the real power of quantum computing. The prime factor contributing to this gap is the large amount of quantum error correction (QEC) that is required during the execution of a quantum algorithm. For serial quantum computers, with just one processing zone, the coherence time of the qubits would have to grow with the increase in number of qubits, which is not realistic. To this end, the researchers have proposed a "Software-Enabled Vertical Integration and Co-Design", which helps in developing optimized quantum compilers and produce easily verifiable solutions. The other option is to either increase the coherence time, decrease the time per quantum gate operation. However, both of these does not seem to be feasible, because both will lead to increase in execution time, albeit reducing the quantum error rate. Therefore, the feasible solution is to parallelize the quantum information processing (QIP), or the quantum instructions. In this paper, we design a simple quantum instruction set architecture (QISA) and a quantum pipelined architecture (QuPA). The proposed QISA is very similar to the classical instruction set architecture, except that the opcode is initially in an equal superposed state. Also the proposed QISA is grouped based on a certain common prefix, which helps to decode a particular (or group of) operation(s) with a higher probability. We demonstrate how the proposed QISA can be executed over the proposed QuPA with much less quantum cost compared to a general serial architecture. We show that the proposed QuPA has a gate cost of O(2m) compared to the gate cost of the serial architecture, which is O(2n), where m ≤ n.
Recent developments in engineering and algorithms have made real-world applications in quantum computing possible in the near future. Existing quantum programming languages and compilers use a quantum assembly language composed of 1- and 2-qubit (quantum bit) gates. Quantum compiler frameworks translate this quantum assembly to electric signals (called control pulses) that implement the specified computation on specific physical devices. However, there is a mismatch between the operations defined by the 1- and 2-qubit logical ISA and their underlying physical implementation, so the current practice of directly translating logical instructions into control pulses results in inefficient, high-latency programs. To address this inefficiency, we propose a universal quantum compilation methodology that aggregates multiple logical operations into larger units that manipulate up to 10 qubits at a time. Our methodology then optimizes these aggregates by (1) finding commutative intermediate operations that result in more efficient schedules and (2) creating custom control pulses optimized for the aggregate (instead of individual 1- and 2-qubit operations). Compared to the standard gate-based compilation, the proposed approach realizes a deeper vertical integration of high-level quantum software and low-level, physical quantum hardware. We evaluate our approach on important near-term quantum applications on simulations of superconducting quantum architectures. Our proposed approach provides a mean speedup of 5×, with a maximum of 10×. Because latency directly affects the feasibility of quantum computation, our results not only improve performance but also have the potential to enable quantum computation sooner than otherwise possible.
The performance of current quantum hardware is severely limited. While expanding the quantum ISA with high-fidelity, expressive basis gates is a key path forward, it imposes significant gate calibration overhead and complicates compiler optimization. As a result, even though more powerful ISAs have been designed, their use remains largely conceptual rather than practical.
To move beyond these hurdles, we introduce the concept of "reconfigurable quantum instruction set computers" (ReQISC), which incorporates: (1) a unified microarchitecture capable of directly implementing arbitrary 2Q gates equivalently, i.e., SU(4) modulo 1Q rotations, with theoretically optimal gate durations given any 2Q coupling Hamiltonians; (2) a compilation framework tailored to ReQISC primitives for end-to-end synthesis and optimization, comprising a program-aware pass that refines high-level representations, a program-agnostic pass for aggressive circuit-level optimization, and an SU(4)-aware routing pass that minimizes hardware mapping overhead.
We detail the hardware implementation to demonstrate the feasibility, in terms of both pulse control and calibration of this superior gate scheme on realistic hardware. By leveraging the expressivity of SU(4) and the time minimality realized by the underlying microarchitecture, the SU(4)-based ISA achieves remarkable performance, with a 4.97-fold reduction in average pulse duration to implement arbitrary 2Q gates, compared to the usual CNOT/CZ scheme on mainstream flux-tunable transmons. Supported by the end-to-end compiler, ReQISC outperforms the conventional CNOT-ISA, SOTA compiler, and pulse implementation counterparts, in significantly reducing 2Q gate counts, circuit depth, pulse duration, qubit mapping overhead, and program fidelity losses. For the first time, ReQISC makes the theoretical benefits of continuous ISAs practically feasible.