The design and architecture of a quantum instruction set are paramount to the performance of a quantum computer. This work introduces a gate scheme for qubits with XX + YY coupling that directly and efficiently realizes any two-qubit gate up to single-qubit gates. First, this scheme enables high-fidelity execution of quantum operations, especially when decoherence is the primary error source. Second, since the scheme spans the entire SU(4) group of two-qubit gates, we can use it to attain the optimal two-qubit gate count for algorithm implementation. These two advantages in synergy give rise to a quantum Complex yet Reduced Instruction Set Computer (CRISC). Though the gate scheme is compact, it supports a comprehensive array of quantum operations. This may seem paradoxical but is realizable due to the fundamental differences between quantum and classical computer architectures.
The design and architecture of a quantum instruction set are paramount to the performance of a quantum computer. This work introduces a gate scheme for qubits with XX + YY coupling that directly and efficiently realizes any two-qubit gate up to single-qubit gates. First, this scheme enables high-fidelity execution of quantum operations, especially when decoherence is the primary error source. Second, since the scheme spans the entire SU(4) group of two-qubit gates, we can use it to attain the optimal two-qubit gate count for algorithm implementation. These two advantages in synergy give rise to a quantum Complex yet Reduced Instruction Set Computer (CRISC). Though the gate scheme is compact, it supports a comprehensive array of quantum operations. This may seem paradoxical but is realizable due to the fundamental differences between quantum and classical computer architectures.
The set of quantum logic gates that can be easily implemented is fundamental to the performance of quantum computers, as it governs the accuracy of basic quantum operations and dictates the complexity of implementing quantum algorithms. Traditional approaches to extending gate sets often require operating devices outside the ideal parameter regimes used to realize qubits, leading to increased control complexity while offering only a limited set of gates. Here we experimentally demonstrate a unified and versatile gate scheme capable of generating arbitrary two-qubit gates using only an exchange interaction and qubit driving on a superconducting quantum processor. We achieve high fidelities averaging 99.38% across a wide range of commonly used two-qubit unitaries, enabling precise multipartite entangled state preparation. Furthermore, we successfully produce a B gate, which efficiently synthesizes the entire family of two-qubit gates. Our results establish that fully exploiting the capabilities of the exchange interaction can yield a comprehensive and highly accurate gate set. With maximum expressivity, optimal gate time, demonstrated high fidelity and easy adaption to other quantum platforms, our unified control scheme offers the prospect of improved performance in quantum hardware and algorithm development. The efficiency of a quantum computer depends on which basic operations it can implement. Now a scheme that can implement any two-qubit logic gate has been demonstrated on a superconducting architecture.
The existence of algorithm to machine gap has been accepted by the quantum computing domain experts, as the research community is struggling to realize the real power of quantum computing. The prime factor contributing to this gap is the large amount of quantum error correction (QEC) that is required during the execution of a quantum algorithm. For serial quantum computers, with just one processing zone, the coherence time of the qubits would have to grow with the increase in number of qubits, which is not realistic. To this end, the researchers have proposed a "Software-Enabled Vertical Integration and Co-Design", which helps in developing optimized quantum compilers and produce easily verifiable solutions. The other option is to either increase the coherence time, decrease the time per quantum gate operation. However, both of these does not seem to be feasible, because both will lead to increase in execution time, albeit reducing the quantum error rate. Therefore, the feasible solution is to parallelize the quantum information processing (QIP), or the quantum instructions. In this paper, we design a simple quantum instruction set architecture (QISA) and a quantum pipelined architecture (QuPA). The proposed QISA is very similar to the classical instruction set architecture, except that the opcode is initially in an equal superposed state. Also the proposed QISA is grouped based on a certain common prefix, which helps to decode a particular (or group of) operation(s) with a higher probability. We demonstrate how the proposed QISA can be executed over the proposed QuPA with much less quantum cost compared to a general serial architecture. We show that the proposed QuPA has a gate cost of O(2m) compared to the gate cost of the serial architecture, which is O(2n), where m ≤ n.
Scaling bottlenecks the making of digital quantum computers, posing challenges from both the quantum and the classical components. We present a classical architecture to cope with a comprehensive list of the latter challenges all at once , and implement it fully in an end-to-end system by integrating a multi-core RISC-V CPU with our in-house control electronics. Our architecture enables scalable, high-precision control of large quantum processors and accommodates evolving requirements of quantum hardware. A central feature is a microarchitecture executing quantum operations in parallel on arbitrary predefined qubit groups. Another key feature is a reconfigurable quantum instruction set that supports easy qubit re-grouping and instructions extensions. As a demonstration, we implement the widely-studied surface code quantum computing workflow, which is instructive for being demanding on both the controllers and the integrated classical computation. Our design, for the first time, reduces instruction issuing and transmission costs to constants, which do not scale with the number of qubits, without adding any overheads in decoding or dispatching. Our system uses a dedicated general-purpose CPU for both qubit control and classical computation, including syndrome decoding. Implementing recent theoretical proposals as decoding firmware that parallelizes general inner decoders, we can achieve unprecedented decoding capabilities of up to distances 47 and 67 with the currently available systems-on-chips for physical error rate p = 0.001 and p = 0.0001, respectively, all in just 1 μs.
The quantum instruction set (QIS) is defined as the quantum gates that are physically realizable by controlling the qubits in quantum hardware. Compiling quantum circuits into the product of the gates in a properly defined QIS is a fundamental step in quantum computing. We here propose the quantum variational instruction set (QuVIS) formed by flexibly designed multiqubit gates for higher speed and accuracy of quantum computing. The controlling of qubits for realizing the gates in a QuVIS is variationally achieved using the fine-grained time optimization algorithm. Significant reductions in both the error accumulation and time cost are demonstrated in realizing the swaps of multiple qubits and quantum Fourier transformations, compared with the compiling by a standard QIS such as the quantum microinstruction set (QuMIS, formed by several one- and two-qubit gates including one-qubit rotations and controlled-not gates). With the same requirement on quantum hardware, the time cost for QuVIS is reduced to less than one-half of that for QuMIS. Simultaneously, the error is suppressed algebraically as the depth of the compiled circuit is reduced. As a general compiling approach with high flexibility and efficiency, QuVIS can be defined for different quantum circuits and be adapted to the quantum hardware with different interactions.
Quantum computing holds great promise for both scientific discovery and commercial applications. Superconducting quantum systems have become one of the leading architectures for large-scale quantum computing. Towards realizing practical quantum computing, improving two-qubit gate fidelity is a crucial task. It is relevant for both near-term pre-fault-tolerant quantum computers and future fault-tolerant quantum computers. This dissertation aims to provide a comprehensive study of two-qubit gates in superconducting systems. The major focus is on improving gate fidelity via using different drive schemes and coupler designs. The dissertation contains two primary original contributions. First, a novel method for implementing continuous fSim gates is proposed and analyzed in detail. The fSim gate set is a family of gates that combines iSWAP gate and CPHASE gate into one gate with variable rotation angles and conditional phase. This gate set is particularly interesting for quantum simulation of fermionic systems. Second, a theoretical framework for multi-mode couplers is developed. A multi-mode coupler design is proposed to enable fully localized decoupling among qubits and independent control of qubit-qubit interactions in different excitation subspaces. An example of two qubits coupled by a two-mode coupler is studied in detail. Building on the fSim gate theory and multi-mode coupler design, several future research directions are outlined. Pulse-level algorithms for simulating electronic systems are discussed as a key application of fSim gates. A three-mode coupler architecture is further introduced. In addition, the importance of incorporating open-system dynamics for accurate modeling of coupler behavior and gate performance is emphasized. Finally, a unified framework for modeling superconducting quantum processors is proposed, providing a systematic way to compare gate fidelities across theoretical approaches and ultimately guide improvements in quantum hardware performance.
The equivalence between the instructions used to define programs and the input data on which the instructions operate is a basic principle of classical computer architectures and programming. Replacing classical data with quantum states enables fundamentally new computational capabilities with scaling advantages for many applications, and numerous models have been proposed for realizing quantum computation. However, within each of these models, the quantum data are transformed by a set of gates that are compiled using solely classical information. Conventional quantum computing models thus break the instruction-data symmetry: classical instructions and quantum data are not directly interchangeable. In this work, we use a density matrix exponentiation protocol to execute quantum instructions on quantum data. In this approach, a fixed sequence of classically-defined gates performs an operation that uniquely depends on an auxiliary quantum instruction state. Our demonstration relies on a 99.7% fidelity controlled-phase gate implemented using two tunable superconducting transmon qubits, which enables an algorithmic fidelity surpassing 90% at circuit depths exceeding 70. The utilization of quantum instructions obviates the need for costly tomographic state reconstruction and recompilation, thereby enabling exponential speedup for a broad range of algorithms, including quantum principal component analysis, the measurement of entanglement spectra, and universal quantum emulation.