The existence of algorithm to machine gap has been accepted by the quantum computing domain experts, as the research community is struggling to realize the real power of quantum computing. The prime factor contributing to this gap is the large amount of quantum error correction (QEC) that is required during the execution of a quantum algorithm. For serial quantum computers, with just one processing zone, the coherence time of the qubits would have to grow with the increase in number of qubits, which is not realistic. To this end, the researchers have proposed a "Software-Enabled Vertical Integration and Co-Design", which helps in developing optimized quantum compilers and produce easily verifiable solutions. The other option is to either increase the coherence time, decrease the time per quantum gate operation. However, both of these does not seem to be feasible, because both will lead to increase in execution time, albeit reducing the quantum error rate. Therefore, the feasible solution is to parallelize the quantum information processing (QIP), or the quantum instructions. In this paper, we design a simple quantum instruction set architecture (QISA) and a quantum pipelined architecture (QuPA). The proposed QISA is very similar to the classical instruction set architecture, except that the opcode is initially in an equal superposed state. Also the proposed QISA is grouped based on a certain common prefix, which helps to decode a particular (or group of) operation(s) with a higher probability. We demonstrate how the proposed QISA can be executed over the proposed QuPA with much less quantum cost compared to a general serial architecture. We show that the proposed QuPA has a gate cost of O(2m) compared to the gate cost of the serial architecture, which is O(2n), where m ≤ n.
The existence of algorithm to machine gap has been accepted by the quantum computing domain experts, as the research community is struggling to realize the real power of quantum computing. The prime factor contributing to this gap is the large amount of quantum error correction (QEC) that is required during the execution of a quantum algorithm. For serial quantum computers, with just one processing zone, the coherence time of the qubits would have to grow with the increase in number of qubits, which is not realistic. To this end, the researchers have proposed a "Software-Enabled Vertical Integration and Co-Design", which helps in developing optimized quantum compilers and produce easily verifiable solutions. The other option is to either increase the coherence time, decrease the time per quantum gate operation. However, both of these does not seem to be feasible, because both will lead to increase in execution time, albeit reducing the quantum error rate. Therefore, the feasible solution is to parallelize the quantum information processing (QIP), or the quantum instructions. In this paper, we design a simple quantum instruction set architecture (QISA) and a quantum pipelined architecture (QuPA). The proposed QISA is very similar to the classical instruction set architecture, except that the opcode is initially in an equal superposed state. Also the proposed QISA is grouped based on a certain common prefix, which helps to decode a particular (or group of) operation(s) with a higher probability. We demonstrate how the proposed QISA can be executed over the proposed QuPA with much less quantum cost compared to a general serial architecture. We show that the proposed QuPA has a gate cost of O(2m) compared to the gate cost of the serial architecture, which is O(2n), where m ≤ n.
A widely-used quantum programming paradigm comprises of both the data How and control How. Existing quantum hardware cannot well support the control How, significantly limiting the range of quantum software executable on the hardware. By analyzing the constraints in the control microarchitecture, we found that existing quantum assembly languages are either too high-level or too restricted to support comprehensive How control on the hardware. Also, as observed with the quantum microinstruction set QuMIS [1], the quantum instruction set architecture (QISA) design may suffer from limited scalability and Hexibility because of microarchitectural constraints. It is an open challenge to design a scalable and Hexible QISA which provides a comprehensive abstraction of the quantum hardware. In this paper, we propose an executable QISA, called eQASM, that can be translated from quantum assembly language (QASM), supports comprehensive quantum program How control, and is executed on a quantum control microarchitecture. With efficient timing specification, single-operation-multiple-qubit execution, and a very-long-instruction-word architecture, eQASM presents better scalability than QuMIS. The definition of eQASM focuses on the assembly level to be expressive. Quantum operations are configured at compile time instead of being defined at QISA design time. We instantiate eQASM into a 32-bit instruction set targeting a seven-qubit superconducting quantum processor. We validate our design by performing several experiments on a two-qubit quantum processor.
Quantum computing promises an effective way to solve targeted problems that are classically intractable. Among them, quantum computers built with superconducting qubits are considered one of the most advanced technologies, but they suffer from short coherence times. This can get exaggerated when they are controlled directly by general-purpose host machines, which in turn leads to the loss of quantum information. To mitigate this, we need quantum control processors (QCPs) positioned between quantum processing units (QPUs) and host machines to reduce latencies. However, existing QCPs are built on top of designs with no or inefficient scalability, requiring a large number of instructions when scaling to more qubits. In addition, interactions between current QCPs and host machines require frequent data transmissions and offline computations to obtain final results from hundreds of repeated executions, which limits the performance of quantum computers.In this paper, we propose a QCP — called HiSEP-Q — featuring a novel quantum instruction set architecture (QISA) and its microarchitecture implementation. For efficient control, we utilize mixed-type addressing modes and mixed-length instructions in HiSEP-Q, which provides an efficient way to concurrently address more than 100 qubits. Further, for efficient read-out and analysis, we develop a novel onboard accumulation and sorting unit, which eliminates the data transmission of raw data between the QCPs and host machines and enables real-time result processing. Compared to the state-of-the-art, our proposed QISA achieves at least 62% and 28% improvements in encoding efficiency with real and synthetic quantum circuits, respectively. We also validate the microarchitecture on a field-programmable gate array (FPGA), which exhibits low power and resource consumption, even as the number of qubits scales to 100. Both hardware and ISA evaluations demonstrate that HiSEP-Q features high scalability and efficiency toward the number of controlled qubits.
The design and architecture of a quantum instruction set are paramount to the performance of a quantum computer. This work introduces a gate scheme for qubits with XX + YY coupling that directly and efficiently realizes any two-qubit gate up to single-qubit gates. First, this scheme enables high-fidelity execution of quantum operations, especially when decoherence is the primary error source. Second, since the scheme spans the entire SU(4) group of two-qubit gates, we can use it to attain the optimal two-qubit gate count for algorithm implementation. These two advantages in synergy give rise to a quantum Complex yet Reduced Instruction Set Computer (CRISC). Though the gate scheme is compact, it supports a comprehensive array of quantum operations. This may seem paradoxical but is realizable due to the fundamental differences between quantum and classical computer architectures.
Scaling fault-tolerant quantum computing (FTQC) requires orchestrating millions of operations continuously across a tightly coupled classical-quantum control stack. A critical challenge in this orchestration is determining the optimal hardware-software boundary, i.e., the Quantum Instruction Set Architecture (QISA). We focus on cryogenic, fixed-connectivity qubit platforms, such as superconducting and topological Majorana qubits. For these, existing QISA choices either operate at too low a level, violating cryogenic thermal budgets at scale, or at too high a level, imposing unrealizable complexity on the control engine. To reason about these tradeoffs, we introduce the ARIES instruction set hierarchy, which categorizes QISAs into distinct abstraction levels. To systematically evaluate these levels, we develop an end-to-end evaluation toolflow featuring a cycle-accurate classical driver and hardware engine simulator. Using eight quantum applications across superconducting and topological qubit platforms, we measure instruction bandwidth, transceiver power dissipation, and measurement processing overheads. We demonstrate that while physical-level abstractions exceed the thermal limits of dilution refrigerators by orders of magnitude, canonical-level abstractions significantly underestimate hardware routing congestion and execution runtimes. Our Level 4 QISA (local logical operations) offers an optimal architectural balance. As quantum hardware platforms scale toward FTQC in the coming years, our findings provide concrete architectural guidance for the design of their classical control stacks and instruction interfaces.
Building a quantum computer is not only about having qubits or quantum processors, analogously to classical computers are not only based on transistors or integrated circuits. Accordingly, in the very recent times, a few unique research groups in academia and companies have been exploring and proposing high-level and low-level programming languages, compilers, microarchitecture and instruction set architectures for quantum computation as well as different computer architecture approaches. In other words, developing a quantum computer requires bridging quantum applications and quantum devices. This talk will address the main challenges of building a scalable full-stack quantum computing system followed by a discussion on its architecture focusing on fault tolerance and compilation of quantum algorithms on NISQ devices. I will also provide my vision on how the research community could accelerate the process towards building such a scalable quantum machine, potentially through vertical cross-layer co-design structured methodologies.
As quantum computers continue to improve and support larger, more complex computations, smart control hardware and compilers are needed to efficiently leverage the capabilities of these systems.
This paper introduces a novel approach to enhance the execution of quantum algorithms on distributed quantum systems. The proposed method involves the development of a hardware design that supports parallel instruction execution and a compiler that modifies the order of instructions to increase parallelism opportunities. The hardware design can be flexibly configured to facilitate parallel execution of instructions that have identical parameters. Furthermore, the compiler uses the underlying hardware constraints to intelligently reorder and decompose instructions to avoid dependencies.
The compiler, hardware, and their combination are evaluated using a runtime calculator and a benchmark quantum algorithm set. The results demonstrate a significant speedup, achieving a maximum average speedup of 16.5x and a maximum single-benchmark speedup of 56.2x relative to a baseline, serial execution model. Furthermore, we show a speedup can be obtained across all benchmarks using any of the proposed hardware schemes, although the degree of speedup is largely dependent on the type of quantum algorithm. Taken together, the results of this paper represent a significant step towards realizing high-performance quantum computing systems.