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arXiv:2511.14306 · Physica Scripta

Parallelizing Program Execution on Distributed Quantum Systems via Compiler/Hardware Co-Design

Folkert de Ronde, Alexander Knapen, Stephan Wong, Sebastian Feld

quant-phSubmitted Nov 18, 2025• Announced Nov 19, 2025• 0 citations
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Abstract

As quantum computers continue to improve and support larger, more complex computations, smart control hardware and compilers are needed to efficiently leverage the capabilities of these systems. This paper introduces a novel approach to enhance the execution of quantum algorithms on distributed quantum systems. The proposed method involves the development of a hardware design that supports parallel instruction execution and a compiler that modifies the order of instructions to increase parallelism opportunities. The hardware design can be flexibly configured to facilitate parallel execution of instructions that have identical parameters. Furthermore, the compiler uses the underlying hardware constraints to intelligently reorder and decompose instructions to avoid dependencies. The compiler, hardware, and their combination are evaluated using a runtime calculator and a benchmark quantum algorithm set. The results demonstrate a significant speedup, achieving a maximum average speedup of 16.5x and a maximum single-benchmark speedup of 56.2x relative to a baseline, serial execution model. Furthermore, we show a speedup can be obtained across all benchmarks using any of the proposed hardware schemes, although the degree of speedup is largely dependent on the type of quantum algorithm. Taken together, the results of this paper represent a significant step towards realizing high-performance quantum computing systems.

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18 pages, 15 figures

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As quantum computers continue to improve and support larger, more complex computations, smart control hardware and compilers are needed to efficiently leverage the capabilities of these systems.
This paper introduces a novel approach to enhance the execution of quantum algorithms on distributed quantum systems. The proposed method involves the development of a hardware design that supports parallel instruction execution and a compiler that modifies the order of instructions to increase parallelism opportunities. The hardware design can be flexibly configured to facilitate parallel execution of instructions that have identical parameters. Furthermore, the compiler uses the underlying hardware constraints to intelligently reorder and decompose instructions to avoid dependencies.
The compiler, hardware, and their combination are evaluated using a runtime calculator and a benchmark quantum algorithm set. The results demonstrate a significant speedup, achieving a maximum average speedup of 16.5x and a maximum single-benchmark speedup of 56.2x relative to a baseline, serial execution model. Furthermore, we show a speedup can be obtained across all benchmarks using any of the proposed hardware schemes, although the degree of speedup is largely dependent on the type of quantum algorithm. Taken together, the results of this paper represent a significant step towards realizing high-performance quantum computing systems.
Quantum computing promises revolutionary advancements across various fields, but its practical realization hinges on overcoming significant challenges in algorithm execution. Traditional hardware-software co-design approaches for quantum computing often rely on pre-defined architectures and compilation strategies, which can be suboptimal for diverse quantum algorithms. This paper proposes an adaptive hardware-software co-design framework that dynamically adjusts the quantum computing system's configuration – encompassing both hardware architecture and software compilation – in response to the specific requirements of the algorithm being executed. The core claim is that optimized co-design is pivotal for efficient quantum algorithm execution. This framework leverages a dynamic optimization loop, continuously monitoring algorithm performance and adjusting parameters such as qubit connectivity, gate set selection, and compilation strategies. The system utilizes a mathematical model to represent the algorithm's computational demands and hardware capabilities, enabling real-time adaptation. This approach moves beyond static design methodologies, offering a pathway towards significantly improved performance and resource utilization in quantum computing systems. The framework's ability to adapt in real-time represents a crucial step towards unlocking the full potential of quantum algorithms.
Quantum computing is expected to become a foundational technology for solving problems that exceed the capabilities of classical systems. As quantum algorithms and hardware technologies continue to advance, the need for scalable architectures becomes increasingly clear. Distributed quantum computing offers a promising path forward by interconnecting multiple smaller processors into a larger, more powerful system. However, distributed quantum computing introduces significant circuit depth overhead, as logical operations are typically decomposed into sequential physical procedures that require entanglement generation. These sequential operations limit the reliability of quantum algorithms in the NISQ era due to noise. In this work, we present a compiler that integrates logical-to-physical decomposition with depth-aware rescheduling to reduce the execution cost of distributed quantum circuits. The compiler identifies sequences of logical CNOT gates that share a control or target qubit, reschedules them into parallel instruction groups, and applies decompositions that allow multiple gates to be executed simultaneously using distributed shared entanglement resources. An algorithm is proposed that ensures parallelism is created when possible while keeping logical equivalence and that circuit depth is never increased. Benchmark results demonstrate that the compiler consistently reduces circuit depth for circuits containing inherently sequential CNOT structures, while leaving already-parallel circuits unchanged. These results highlight the value of combining scheduling and hardware-aware decomposition, and establish the compiler as a practical tool for improving the fidelity of distributed quantum computations.
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This paper presents a novel approach to distributed quantum algorithm compilation, termed Adaptive Distributed Quantum Algorithm Compilation (ADQAC). The core idea is to develop a system capable of automatically compiling and optimizing quantum algorithms for execution on distributed quantum hardware, adapting to the specific characteristics and resource constraints of each node. We leverage reinforcement learning (RL) to dynamically adjust the algorithm's execution sequence, gate selection, and resource allocation based on real-time performance metrics gathered from the quantum hardware. This approach addresses the significant challenges of translating high-level quantum algorithms into efficient, executable code for heterogeneous distributed quantum computing environments. The system aims to maximize algorithm fidelity while minimizing communication overhead and resource utilization. The proposed ADQAC framework offers a potential pathway toward realizing the full potential of distributed quantum computation by enabling algorithms to intelligently adapt to the limitations and opportunities presented by the underlying hardware.
Recent developments in engineering and algorithms have made real-world applications in quantum computing possible in the near future. Existing quantum programming languages and compilers use a quantum assembly language composed of 1- and 2-qubit (quantum bit) gates. Quantum compiler frameworks translate this quantum assembly to electric signals (called control pulses) that implement the specified computation on specific physical devices. However, there is a mismatch between the operations defined by the 1- and 2-qubit logical ISA and their underlying physical implementation, so the current practice of directly translating logical instructions into control pulses results in inefficient, high-latency programs. To address this inefficiency, we propose a universal quantum compilation methodology that aggregates multiple logical operations into larger units that manipulate up to 10 qubits at a time. Our methodology then optimizes these aggregates by (1) finding commutative intermediate operations that result in more efficient schedules and (2) creating custom control pulses optimized for the aggregate (instead of individual 1- and 2-qubit operations). Compared to the standard gate-based compilation, the proposed approach realizes a deeper vertical integration of high-level quantum software and low-level, physical quantum hardware. We evaluate our approach on important near-term quantum applications on simulations of superconducting quantum architectures. Our proposed approach provides a mean speedup of 5×5\times5×, with a maximum of 10×10\times10×. Because latency directly affects the feasibility of quantum computation, our results not only improve performance but also have the potential to enable quantum computation sooner than otherwise possible.
The Quantum Control Processor (QCP) bridges the gap between compiler toolchains and control electronics, and is responsible for translating compiled quantum circuits into executable instructions that directly manipulate qubits and handle measurement feedback. However, existing designs rely primarily on customized instruction sets, limiting design reuse and requiring significant effort to build supporting toolchains. Furthermore, efficiently addressing qubits and scheduling operations in highly scalable scenarios remains a critical challenge. In this work, we present a vectorized quantum control approach built upon the RISC-V Vector (RVV) engine with a quantum-oriented extension. Leveraging the high parallelism of RVV, our approach can address up to 128 qubits in a single instruction. We also embed parameterized rotation information into the instruction set, enabling dynamic tuning of gate rotations in hybrid quantum-classical programs. To support mid-circuit measurements, we design a hardware-based halt-resume protocol that resumes pipeline execution within 80 nsnsns of receiving the measurement result. Comprehensive evaluation using both RISC-V toolchains and FPGA prototypes demonstrates that our design achieves up to 2.52×\times× speedup over the baseline in program execution time, with excellent scalability.