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Superconductor-to-semiconductor communication interface module for system integration of very high-speed superconductor digital electronics

S. Wünsch, J. Flamm, R. Schwemlein, E. Crocoll, M. Siegel, Hannes Töpfer, Thomas Ortlepp, Friedrich Uhlmann

Published Jan 1, 2004• 0 citations
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High-speed digital data links from 4-K superconductor electronics to room temperature are challenging due to the fact that energy/bit for single flux quantum logic is many (six) orders of magnitude lower than that of standard room-temperature logic. Our approach of building an energy-efficient high-speed data link involves a joint electrical-thermal design of a temperature-distributed architecture using different electronic technologies. This differential digital data link design involves superconductor, multiple cryogenic semiconductor and additional room-temperature semiconductor circuitry. The current design involves three cryogenic semiconductor ICs for integration with a multistage cryocooled digital system. The first cryogenic semiconductor IC is designed to operate at 4 K with a power consumption of 0.3 mW and interface directly with the superconductor differential single flux quantum/dc drivers. For testing it, a superconductor carrier chip containing an analog-to-digital converter has been designed for the HYPRES dual-JcJ_{c}Jc​(4.5 and 20kA/cm2\hbox{kA/cm}^{2}kA/cm2) fabrication process.
Superconductor electronics for high-performance computing and high-speed analog-to-digital converters requires multi-channel digital data links. Most difficult is the amplification of the weak signals from the superconductor circuit to the volt level of semiconductor electronics. We developed a hybrid digital interface based on a Josephson latching driver, the so-called Suzuki stack, and a clocked CMOS comparator. The input can be directly triggered by a single flux quantum pulse and the output provides a 1 V CMOS-level signal. In contrast to existing systems, our interface is optimized for ultra-low-power consumption to enable its application for parallel multi-bit data interfaces. We provide evaluation of various types of Suzuki stacks and various CMOS comparators. We present experimental data on the delay of the overall hybrid interface and the total power consumption. The bit-error rate has been measured to be below 10-12. We will discuss the trade-off among circuit robustness, speed, and power consumption.
Interface circuits are the key components that enable the hybrid integration of superconductor and semiconductor digital electronics. The design requirements of superconductor-semiconductor interface circuits vary depending on the application, such as high-performance classical computing, superconducting quantum computing, and digital signal processing. In this survey, various interface circuits are categorized based on the working principle and structure. The superconducting output drivers are explored, which are capable of converting and amplifying, e.g., single flux quantum (SFQ) voltage pulses, to voltage levels that semiconductor circuits can process. Several trade-offs between circuit- and system-level design parameters are examined. Accordingly, parameters such as the data rate, output voltage, power dissipation, layout area, thermal/heat load of cryogenic cables, and bit-error rate are considered.
In this paper, the author describes studies on electronic devices and circuits utilizing both of superconductors and semniconductors. First, a design of an interface circuit composed of Josephson junctions and MOSFETs is described. The Josephson-MOS interface circuit will be used for realizing high-speed data communication between a Josephson digital circuit and a semiconductor one. Second, fabrication and characterization of MOSFETs with superconductive NbN gate electrodes are described. The use of superconductive gates makes it easy to hybridize MOSFETs with Josephson junctions. Finally, studies of Josephson-CMOS hybrid memory circuits are introduced.