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Planar Ion Trap Geometry for Microfabrication

M. J. Madsen, W. K. Hensinger, D. Stick, James Rabchuk, Christopher R. Monroe

Published Jan 1, 2004• 84 citations
OpenAlex

Abstract

Abstract We describe a novel high aspect ratio radiofrequency linear ion trap geometry that is amenable to modern microfabrication techniques. The ion trap electrode structure consists of a pair of stacked conducting cantilevers resulting in confining fields that take the form of fringe fields from parallel plate capacitors. The confining potentials are modeled both analytically and numerically. This ion trap geometry may form the basis for large scale quantum computers or parallel quadrupole mass spectrometers. PACS: 39.25.+k, 03.67.Lx, 07.75.+h, 07.10+Cm 1

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Abstract We describe a novel high aspect ratio radiofrequency linear ion trap geometry that is amenable to modern microfabrication techniques. The ion trap electrode structure consists of a pair of stacked conducting cantilevers resulting in confining fields that take the form of fringe fields from parallel plate capacitors. The confining potentials are modeled both analytically and numerically. This ion trap geometry may form the basis for large scale quantum computers or parallel quadrupole mass spectrometers. PACS: 39.25.+k, 03.67.Lx, 07.75.+h, 07.10+Cm 1
Abstract Scaling trapped-ion quantum computing will require robust trapping of at least hundreds of ions over long periods, while increasing the complexity and functionality of the trap itself. Symmetric three-dimensional (3D) structures enable high trap depth, but microfabrication techniques are generally better suited to planar structures that produce less ideal conditions for trapping. We present an ion trap fabricated on stacked eight-inch wafers in a large-scale micro-electro-mechanical system microfabrication process that provides reproducible traps at a large volume. Electrodes are patterned on the surfaces of two opposing wafers bonded to a spacer, forming a 3D structure with 2.5 μm standard deviation in alignment across the stack. We implement a design achieving a trap depth of 1 eV for a 40Ca+ ion held at 200 μm from either electrode plane. We characterize traps, achieving measurement agreement with simulations to within ±5% for mode frequencies spanning 0.6–3.8 MHz, and evaluate stray electric field across multiple trapping sites. We measure motional heating rates over an extensive range of trap frequencies, and temperatures, observing 40 phonons/s at 1 MHz and 185 K. This fabrication method provides a highly scalable approach for producing a new generation of 3D ion traps.
The prospect of building a quantum information processor underlies many recent advances ion trap fabrication techniques. Potentially, a quantum computer could be constructed from a large array of interconnected ion traps. We report on a micrometer-scale ion trap, fabricated from bulk silicon using micro-electromechanical systems (MEMS) techniques. The trap geometry is relatively simple in that the electrodes lie in a single plane beneath the ions. In such a trap we confine laser-cooled 24Mg+ ions approximately 40 microns above the surface. The fabrication technique and planar electrode geometry together make this approach amenable to scaling up to large trap arrays. In addition we observe that little laser cooling light is scattered by the electrodes.
We investigate a planar ion chip design with a two-dimensional array of linear ion traps for the scalable quantum information processor. The segmented electrodes reside in a single plane on a substrate and a grounded metal plate, a combination of appropriate rf and DC potentials are applied to them for stable ion confinement, and the trap axes are located above the surface at a distance controlled by the electrodes' lateral extent and the substrate's height as discussed. The potential distributions are calculated using static electric field qualitatively. This architecture is conceptually simple and many current microfabrication techniques are feasible for the basic structure. It may provide a promising route for scalable quantum computers.
We describe a new electrode design for a grooved surface-electrode ion trap, which is fabricated in printed-circuit-board technology with segmented electrodes. This design allows a laser beam to get through the central groove to avoid optical access blocking and laser scattering from the ion trap surface. The confining potentials are modeled both analytically and numerically. We optimize the radio frequency (rf) electrodes and dc electrodes to achieve the maximum trap depth for a given ion height above the trap electrodes. We also compare our design with the reality ion chip MI I for practical considerations. Comparison results show that our design is superior to MI I. This ion trap design may form the basis for large scale quantum computers or parallel quadrupole mass spectrometers.
A design is proposed for a novel ion trap quantum processor chip, microfabricated using a process based on planar silica-on-silicon techniques. The trap electrodes are of gold-coated silica and are spaced by highly doped silicon in a monolithic structure. This design allows a unit aspect-ratio trap with an ion-electrode separation below 100 μm, when using current fabrication techniques. The trapping potential is modelled and the operating parameters required to achieve motional frequencies of a few MHz are calculated. RF loss and the resultant heating of the trap chip are not found to be a factor limiting the trap's operation. This monolithic unit aspect-ratio trap is therefore expected to exhibit a deep potential well, high trap efficiency, and a low RF loss, when compared to other microfabricated traps. This technological approach is in principle scaleable to complex devices, and may form the basis for large-scale ion trap quantum processors.
The majority of microfabricated ion traps in use for quantum information processing are of the 2D 'surface-electrode' type or of the 3D 'wafer' type. Surface-electrode traps greatly simplify fabrication and hold the promise of allowing trapped-ion quantum computers to scale via standard semiconductor industry fabrication techniques. However, their geometry constrains them to having much lower trapping efficiency, depth, and harmonicity compared to 3D geometries. Conversely 3D geometries offer superior trap performance but fabrication is more complex, limiting potential to scale. We describe new 'trench' geometries that exist in the design space between these two paradigms. They still allow for a simple, planar electrode layer but with much more favourable trapping properties. We propose such traps could be 3D-printed over a 2D wafer with microfabricated components already integrated into it, thus retaining all the integration techniques and scaling advantages of surface-electrode traps. As a proof of principle we use 2-photon direct laser writing lithography to print the required electrode structures with the proposed geometry.