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Chinese Physics B

A grooved planar ion trap design for scalable quantum information processing

Wei-Bang Ji, Jinyin Wan, Hua-Dong Cheng, Liang Liu

Published Jun 1, 2012• 2 citations
Publisher

Abstract

We describe a new electrode design for a grooved surface-electrode ion trap, which is fabricated in printed-circuit-board technology with segmented electrodes. This design allows a laser beam to get through the central groove to avoid optical access blocking and laser scattering from the ion trap surface. The confining potentials are modeled both analytically and numerically. We optimize the radio frequency (rf) electrodes and dc electrodes to achieve the maximum trap depth for a given ion height above the trap electrodes. We also compare our design with the reality ion chip MI I for practical considerations. Comparison results show that our design is superior to MI I. This ion trap design may form the basis for large scale quantum computers or parallel quadrupole mass spectrometers.

DOI
10.1088/1674-1056/21/6/063701

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We describe a new electrode design for a grooved surface-electrode ion trap, which is fabricated in printed-circuit-board technology with segmented electrodes. This design allows a laser beam to get through the central groove to avoid optical access blocking and laser scattering from the ion trap surface. The confining potentials are modeled both analytically and numerically. We optimize the radio frequency (rf) electrodes and dc electrodes to achieve the maximum trap depth for a given ion height above the trap electrodes. We also compare our design with the reality ion chip MI I for practical considerations. Comparison results show that our design is superior to MI I. This ion trap design may form the basis for large scale quantum computers or parallel quadrupole mass spectrometers.
We investigate a planar ion chip design with a two-dimensional array of linear ion traps for scalable quantum information processing. Qubits are formed from the internal electronic states of trapped 40 Ca + ions. The segmented electrodes reside in a single plane on a substrate and a grounded metal plate separately, a combination of appropriate rf and DC potentials is applied to them for stable ion confinement. Every two adjacent electrodes can generate a linear ion trap in and between the electrodes above the chip at a distance dependent on the geometrical scale and other considerations. The potential distributions are calculated by using a static electric field qualitatively. This architecture provides a conceptually simple avenue to achieving the microfabrication and large-scale quantum computation based on the arrays of trapped ions.
We investigate an effective grooved 2D ion chip design and optimize the ratio between the size of the rf electrodes and the groove. We calculate the optimal size of the groove using the analytical model, which was introduced by House, and the optimum result is obtained. We also obtain the simulated scattering points with the finite element analysis method. The analytical curve and simulated scattering points are coincident with each other. It is shown that this analytical model also fits for the grooved planar ion chip. Thus the optimum grooved 2D planar ion chip design could be obtained. It is effective for scalable quantum information processing.
We investigate a planar ion chip design with a two-dimensional array of linear ion traps for the scalable quantum information processor. The segmented electrodes reside in a single plane on a substrate and a grounded metal plate, a combination of appropriate rf and DC potentials are applied to them for stable ion confinement, and the trap axes are located above the surface at a distance controlled by the electrodes' lateral extent and the substrate's height as discussed. The potential distributions are calculated using static electric field qualitatively. This architecture is conceptually simple and many current microfabrication techniques are feasible for the basic structure. It may provide a promising route for scalable quantum computers.
Ion traps can provide both physical implementation of quantum information processing and direct observation of quantum systems. Recently, surface ion traps have been developed using microfabrication technologies and are considered to be a promising platform for scalable quantum devices. This paper presents detailed guidelines for designing the electrodes of surface ion traps. First, we define and explain the key specifications including trap depth, q-parameter, secular frequency, and ion height. Then, we present a numerical-simulation-based design procedure, which involves determining the basic assumptions, determining the shape and size of the chip, designing the dimensions of the radio frequency (RF) electrode, and analyzing the direct current (DC) control voltages. As an example of this design procedure, we present a case study with tutorial-like explanations. The proposed design procedure can provide a practical guideline for designing the electrodes of surface ion traps.
Abstract We describe the design of a surface-electrode ion trap junction, which is a key element for large-scale ion trap arrays. A bi-objective optimization method is used for designing the electrodes, which maintains the total pseudo-potential curvature while minimizing the axial pseudo-potential gradient along the ion transport path. To facilitate the laser beam delivery for parallel operations in multiple trap zones, we implemented integrated optics on each arm of this X-junction trap. The layout of the trap chip for commercial foundry fabrication is presented. This work suggests routes to improving ion trap junction performance in scalable implementations. Together with integrated optical addressing, this contributes to modular trapped-ion quantum computing in interconnected two-dimensional arrays.
The majority of microfabricated ion traps in use for quantum information processing are of the 2D 'surface-electrode' type or of the 3D 'wafer' type. Surface-electrode traps greatly simplify fabrication and hold the promise of allowing trapped-ion quantum computers to scale via standard semiconductor industry fabrication techniques. However, their geometry constrains them to having much lower trapping efficiency, depth, and harmonicity compared to 3D geometries. Conversely 3D geometries offer superior trap performance but fabrication is more complex, limiting potential to scale. We describe new 'trench' geometries that exist in the design space between these two paradigms. They still allow for a simple, planar electrode layer but with much more favourable trapping properties. We propose such traps could be 3D-printed over a 2D wafer with microfabricated components already integrated into it, thus retaining all the integration techniques and scaling advantages of surface-electrode traps. As a proof of principle we use 2-photon direct laser writing lithography to print the required electrode structures with the proposed geometry.