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Sensors

Guidelines for Designing Surface Ion Traps Using the Boundary Element Method

Seokjun Hong, Minjae Lee, Hongjin Cheon, Taehyun Kim, Dong‐il Cho

Published Apr 28, 2016• 28 citations
Publisher

Abstract

Ion traps can provide both physical implementation of quantum information processing and direct observation of quantum systems. Recently, surface ion traps have been developed using microfabrication technologies and are considered to be a promising platform for scalable quantum devices. This paper presents detailed guidelines for designing the electrodes of surface ion traps. First, we define and explain the key specifications including trap depth, q-parameter, secular frequency, and ion height. Then, we present a numerical-simulation-based design procedure, which involves determining the basic assumptions, determining the shape and size of the chip, designing the dimensions of the radio frequency (RF) electrode, and analyzing the direct current (DC) control voltages. As an example of this design procedure, we present a case study with tutorial-like explanations. The proposed design procedure can provide a practical guideline for designing the electrodes of surface ion traps.

DOI
10.3390/s16050616

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Ion traps can provide both physical implementation of quantum information processing and direct observation of quantum systems. Recently, surface ion traps have been developed using microfabrication technologies and are considered to be a promising platform for scalable quantum devices. This paper presents detailed guidelines for designing the electrodes of surface ion traps. First, we define and explain the key specifications including trap depth, q-parameter, secular frequency, and ion height. Then, we present a numerical-simulation-based design procedure, which involves determining the basic assumptions, determining the shape and size of the chip, designing the dimensions of the radio frequency (RF) electrode, and analyzing the direct current (DC) control voltages. As an example of this design procedure, we present a case study with tutorial-like explanations. The proposed design procedure can provide a practical guideline for designing the electrodes of surface ion traps.
We describe a new electrode design for a grooved surface-electrode ion trap, which is fabricated in printed-circuit-board technology with segmented electrodes. This design allows a laser beam to get through the central groove to avoid optical access blocking and laser scattering from the ion trap surface. The confining potentials are modeled both analytically and numerically. We optimize the radio frequency (rf) electrodes and dc electrodes to achieve the maximum trap depth for a given ion height above the trap electrodes. We also compare our design with the reality ion chip MI I for practical considerations. Comparison results show that our design is superior to MI I. This ion trap design may form the basis for large scale quantum computers or parallel quadrupole mass spectrometers.
Abstract We present a design study into an ion trap electrode geometry for applying near-field microwave two-qubit gates. This design features an ‘S’-shaped meander electrode to passively null the microwave field. It has ground planes separating the meander electrode from all of the DC and single-qubit microwave electrodes, which should reduce the sensitivity of the microwave field distribution to the boundary conditions of these electrodes. We show that it is possible to design a single-layer trap with this geometry such that the simulated microwave field null overlaps with the RF field null, and that the positions of these nulls can be simulated to a precision of 100 nm with moderate computing resources. We also show that such a trap can be designed such that ion chains can be trapped, transported and split with feasible DC and RF voltages. While this particular design is optimized for 43^{43}43 43 Ca +^{+}+ + ions, our approach could be applied to other ions by changing the microwave frequency to match the corresponding qubit transition frequency.
Abstract Junctions are fundamental elements that support qubit locomotion in two-dimensional ion trap arrays and enhance connectivity in emerging trapped-ion quantum computers. In surface ion traps they have typically been implemented by shaping radio frequency (RF) electrodes in a single plane to minimize the disturbance to the pseudopotential. However, this method introduces issues related to RF lead routing that can increase power dissipation and the likelihood of voltage breakdown. Here, we propose and simulate a novel two-layer junction design incorporating two perpendicularly rotoreflected (rotated, then reflected) linear ion traps. The traps are vertically separated, and create a trapping potential between their respective planes. The orthogonal orientation of the RF electrodes of each trap relative to the other provides perpendicular axes of confinement that can be used to realize transport in two dimensions. While this design introduces manufacturing and operating challenges, as now two separate structures have to be precisely positioned relative to each other in the vertical direction and optical access from the top is obscured, it obviates the need to route RF leads below the top surface of the trap and eliminates the pseudopotential bumps that occur in typical junctions. In this paper the stability of idealized ion transfer in the new configuration is demonstrated, both by solving the Mathieu equation analytically to identify the stable regions and by numerically modeling ion dynamics. Our novel junction layout has the potential to enhance the flexibility of microfabricated ion trap control to enable large-scale trapped-ion quantum computing.
Microfabricated surface-electrode traps are a scalable platform for trapped-ion quantum processors. Recent advances in fabrication techniques have enabled the design of increasingly complex multi-layer structures. Yet the control electrodes remain mostly unchanged and of rectangular shape. We systematically analyze asymmetric inner control electrode shapes for simultaneous axial and radial control in multi-layer surface traps, characterize and compare a selection of different shapes, and verify their capabilities in realistic use-case scenarios for ion transport and micromotion compensation. Eliminating the need for the commonly used additional outer control electrodes, asymmetric inner control electrodes increase the compactness and space efficiency of surface-electrode traps while concurrently reducing the number of control signals. The improved control voltage efficiency of using solely inner electrodes enables the device's entire direct-current (DC) supply to be provided by integrated Cryo-CMOS circuits, further enhancing the scalability of the processor.
We investigate a planar ion chip design with a two-dimensional array of linear ion traps for the scalable quantum information processor. The segmented electrodes reside in a single plane on a substrate and a grounded metal plate, a combination of appropriate rf and DC potentials are applied to them for stable ion confinement, and the trap axes are located above the surface at a distance controlled by the electrodes' lateral extent and the substrate's height as discussed. The potential distributions are calculated using static electric field qualitatively. This architecture is conceptually simple and many current microfabrication techniques are feasible for the basic structure. It may provide a promising route for scalable quantum computers.
Ion trap is a promising approach to realizing scalable quantum computer as it presents high coherence time. Silicon, due to its manufacturability, is being considered as a potential substrate to fabricate complex ion-trap designs towards trap miniaturization and on-chip integration of electronics and optics. However, Si ion traps need proper structural design to reduce the substrate RF loss. In this paper, high-resistivity Si substrate materials has been utilized to fabricate surface electrode ion trap. Its DC and RF properties has been investigated and compared to the ion trap fabricated on sapphire substrate, which is one of the most established substrate material for trap fabrication.