Microfabricated surface-electrode traps are a scalable platform for trapped-ion quantum processors. Recent advances in fabrication techniques have enabled the design of increasingly complex multi-layer structures. Yet the control electrodes remain mostly unchanged and of rectangular shape. We systematically analyze asymmetric inner control electrode shapes for simultaneous axial and radial control in multi-layer surface traps, characterize and compare a selection of different shapes, and verify their capabilities in realistic use-case scenarios for ion transport and micromotion compensation. Eliminating the need for the commonly used additional outer control electrodes, asymmetric inner control electrodes increase the compactness and space efficiency of surface-electrode traps while concurrently reducing the number of control signals. The improved control voltage efficiency of using solely inner electrodes enables the device's entire direct-current (DC) supply to be provided by integrated Cryo-CMOS circuits, further enhancing the scalability of the processor.
Microfabricated surface-electrode traps are a scalable platform for trapped-ion quantum processors. Recent advances in fabrication techniques have enabled the design of increasingly complex multi-layer structures. Yet the control electrodes remain mostly unchanged and of rectangular shape. We systematically analyze asymmetric inner control electrode shapes for simultaneous axial and radial control in multi-layer surface traps, characterize and compare a selection of different shapes, and verify their capabilities in realistic use-case scenarios for ion transport and micromotion compensation. Eliminating the need for the commonly used additional outer control electrodes, asymmetric inner control electrodes increase the compactness and space efficiency of surface-electrode traps while concurrently reducing the number of control signals. The improved control voltage efficiency of using solely inner electrodes enables the device's entire direct-current (DC) supply to be provided by integrated Cryo-CMOS circuits, further enhancing the scalability of the processor.
Ion traps can provide both physical implementation of quantum information processing and direct observation of quantum systems. Recently, surface ion traps have been developed using microfabrication technologies and are considered to be a promising platform for scalable quantum devices. This paper presents detailed guidelines for designing the electrodes of surface ion traps. First, we define and explain the key specifications including trap depth, q-parameter, secular frequency, and ion height. Then, we present a numerical-simulation-based design procedure, which involves determining the basic assumptions, determining the shape and size of the chip, designing the dimensions of the radio frequency (RF) electrode, and analyzing the direct current (DC) control voltages. As an example of this design procedure, we present a case study with tutorial-like explanations. The proposed design procedure can provide a practical guideline for designing the electrodes of surface ion traps.
Trapped ions within Paul traps have shown to be a promising architecture in the realisation of a quantum information processor together with the ability of providing quantum simulations. Linear Paul traps have demonstrated long coherence times with ions being well isolated from the environment, single and multi-qubit gates and the high fidelity detection of states. The scalability to large number of qubits, incorporating all the previous achievements requires an array of linear ion traps. Microfabrication techniques allow for fabrication and micron level accuracy of the trap electrode dimensions through photolithography techniques. The first part of this thesis presents the experiential setup and trapping of Yb+ ions needed to test large ion trap arrays. This include vacuum systems that can host advanced symmetric and asymmetric ion traps with up to 90 static voltage control electrodes. Demonstration of a single trapped Yb+ ion within a two-layer macroscopic ion trap is presented. with an ion-electrode distance of 310(10) µm. The anomalous heating rate and spectral noise density of the trap was measured, a main form of decoherence within ion traps. The second half of this thesis presents the design and fabrication of multi-layer asymmetric ion traps. This allows for isolated electrodes that cannot be accessed via surface pathways, allowing for higher density of electrodes as well as creating novel trap designs that allow for the potential of quantum simulations to be demonstrated. These include two-dimensional lattices and ring trap designs in which the isolated electrodes provide more control in the ion position. For the microfabrication of these traps I present a novel high-aspect ratio electroplated electrode design that provides shielding of the dielectric layer. This provides a means to mitigate stray electric field due to charge build up on the dielectric surfaces. Electrical testing of the trap structures was performed to test bulk breakdown and surface flashover of the ion trap architectures. Results showed sufficient isolation between electrodes for both radio frequency and static breakdown. Surface flashover voltage measurements over the dielectric layer showed an improvement of more than double over previous results using a new fabrication technique. This will allow for more powerful ion trap chips needed for the next generation of microfabricated ion trap arrays for scalable quantum technologies.
Recent advances in quantum information processing with trapped ions have demonstrated the need for new ion trap architectures capable of holding and manipulating chains of many (>10) ions. Here we present the design and detailed characterization of a new linear trap, microfabricated with scalable complementary metal-oxide-semiconductor (CMOS) techniques, that is well-suited to this challenge. Forty-four individually controlled dc electrodes provide the many degrees of freedom required to construct anharmonic potential wells, shuttle ions, merge and split ion chains, precisely tune secular mode frequencies, and adjust the orientation of trap axes. Microfabricated capacitors on dc electrodes suppress radio-frequency pickup and excess micromotion, while a top-level ground layer simplifies modeling of electric fields and protects trap structures underneath. A localized aperture in the substrate provides access to the trapping region from an oven below, permitting deterministic loading of particular isotopic/elemental sequences via species-selective photoionization. The shapes of the aperture and radio-frequency electrodes are optimized to minimize perturbation of the trapping pseudopotential. Laboratory experiments verify simulated potentials and characterize trapping lifetimes, stray electric fields, and ion heating rates, while measurement and cancellation of spatially-varying stray electric fields permits the formation of nearly-equally spaced ion chains.
Among the various physical systems for quantum bit (qubit) implementation, trapped ion has drawn significant attention due to its long coherence time (in the second range) and high gate fidelity (>99.99% for single qubit gate). After years of careful development, the ion trap, from mechanically assembled linear trap to lithography-defined surface electrode ion trap, is compatible with CMOS fabrication, which opens the door for the high-resolution, high-repeatability and large-scale ion trap manufacturing. To date, the number of fully connected ion qubits in state-of-the-art ion trapping devices is ~10. However, to scale close to or even beyond the noisy intermediate-scale quantum regime (NISQ, ~100 ions), some challenges remain. One such challenge is to maintain the delicate control of multiple components over individual ion with increasing ion number. In such context, this thesis is committed to boost the scalability of ion trap by integrating advanced 3D interconnects (e.g., through silicon via) and other functional modules (e.g., silicon photonics and multilayer metallization). 3D interconnects are integrated in the half space underneath surface electrode, to replace conventional wire bonding that extends out of the surface. Silicon photonics (grating coupler and waveguide) in place of bulk optics and lenses are used for on-chip light routing and emission. Multilayer metallization is used to maintain the overall RF performance and enable high-density interconnection where necessary. Firstly, surface electrode ion traps on different substrates (namely high resistivity silicon, silicon with grounding plane and glass) are designed and fabricated. Standard CMOS back-end-of-line fabrication process on 12-inch wafer platform is employed. The electrical performances of different traps are compared in terms of leakage current (I-V), parasitic capacitance (C-V), on-chip RF loss (S-parameter) and post-packaging resonance. Though the leakage (at the order of 10-8 A) between neighboring electrodes is relatively high, ion trap on glass substrate demonstrates extremely small capacitance (<1 pF) and low RF loss (insertion loss of <0.05 dB at RF frequency of 50 MHz), as compared to the silicon counterparts. This is mainly due to excellent insulation property of glass. Following that, ion trapping test is performed on the glass trap and ions are successfully confined with an averaged lifetime of ~30 minutes (compatible with the 10-11 mbar vacuum level (10-13 Pa)). To simultaneously leverage the dielectric property of glass and the microfabrication compatibility of silicon, the integration of silicon ion trap and glass interposer is performed, between which TSV is used to build the vertical interconnection. Due to the incorporation of TSV, the original wire bonding pads as well as the connection circuits on the surface electrodes can be eliminated. As a result, the form factor of TSV integrated trap is reduced by ~10 times. Correspondingly, the parasitic capacitance between neighboring electrodes is reduced from >24 pF to 3 pF. Similarly, the insertion loss of TSV integrated trap drops to 0.11 dB, in sharp comparison to the previous traps on silicon substrates (up to 2.4 dB). Analytical models are built to respectively characterize the electrode capacitance and overall power loss, and a good agreement is achieved between the model and the measurement result. In addition, since TSV is located in the half space underneath the surface electrodes, the electrodes geometry design is enabled with high flexibility. Meanwhile, the laser obstruction issue due to the stick-out bonding wires has been resolved. In terms of the ion trapping performance, both the heating rate (17 quanta/ms for an axial frequency of 300 kHz) and the lifetime (~30 minutes) of TSV trap are comparable with non-cryogenic traps of similar dimensions. Moreover, a customized CPGA with patterned redistribution layer is used to locate TSV integrated trap directly in the absence of glass interposer, facilitating high-efficiency thermal management and upgrading the packaging flexibility. At the next stage, the co-integration of other functional modules such as silicon photonics and multilayer metallization with TSV trap is investigated. In silicon photonics module, waveguide and grating coupler are on-chip introduced in place of bulk optics to achieve localized light routing and emission. In multilayer metallization module, as a first step, a grounding plane is incorporated into TSV trap to shield the silicon substrate from RF signal, in which specific windows are patterned onto the plane to accommodate TSV and allow the transmission of lights. The compatibility between TSV/multilayer metallization and waveguide/grating coupler for electrical and optical (E/O) signal routing is demonstrated. The preliminary test result based on wafer frontside shows that a ~40% capacitance reduction is achieved, and the insertion loss further drops to 0.06 dB, close to the performance of glass trap. In addition, the simulation results on photonics components indicate that an overall coupling efficiency of <30 dB is obtained from the input fiber to the ion through the photonics circuit. However, the measured power loss for light with wavelength of 1092 nm is as high as 50 dB. The deviation between the simulation and measurement is largely due to the fabrication imperfection and the resultant sloped grating coupler profile. This thesis focuses on the scalability enhancement of ion trap by integrating TSV, silicon photonics and multilayer metallization into conventional ion trap. The results are promising and pave the way for the future large scale quantum computing based on trapped ion.
To increase the power of a trapped-ion quantum information processor, the qubit number, gate speed, and gate fidelity must all increase. All three of these parameters are influenced by the trapping field, which, in turn, depends on the electrode geometry. Here, we consider how the electrode geometry affects the following radial trapping parameters: trap height, harmonicity, depth, and trap frequency. We introduce a simple multi-wafer geometry comprising a ground plane above a surface trap and compare the performance of this trap to a surface trap and a multi-wafer trap that is a miniaturized version of a linear Paul trap. We compare the voltage and frequency requirements needed to reach a desired radial trap frequency and find that the two multi-wafer trap designs provide significant improvements in expected power dissipation over the surface trap design in large part due to increased harmonicity. Finally, we consider the fabrication requirements and the path towards the integration of the necessary optical control. This work provides a basis to optimize future trap designs with scalability in mind.
We report the design, fabrication and characterization of a microfabricated surface-electrode ion trap that supports controlled transport through the two-dimensional intersection of linear trapping zones arranged in a 90° cross. The trap is fabricated with very large scalable integration techniques which are compatible with scaling to a large quantum information processor. The shape of the radio-frequency electrodes is optimized with a genetic algorithm to reduce axial pseudopotential barriers and minimize ion heating during transport. Seventy-eight independent dc control electrodes enable fine control of the trapping potentials. We demonstrate reliable ion transport between junction legs and determine the rate of ion loss due to transport. Doppler-cooled ions survive more than 10 5 round-trip transits between junction legs without loss and more than 65 consecutive round trips without laser cooling.