To increase the power of a trapped-ion quantum information processor, the qubit number, gate speed, and gate fidelity must all increase. All three of these parameters are influenced by the trapping field, which, in turn, depends on the electrode geometry. Here, we consider how the electrode geometry affects the following radial trapping parameters: trap height, harmonicity, depth, and trap frequency. We introduce a simple multi-wafer geometry comprising a ground plane above a surface trap and compare the performance of this trap to a surface trap and a multi-wafer trap that is a miniaturized version of a linear Paul trap. We compare the voltage and frequency requirements needed to reach a desired radial trap frequency and find that the two multi-wafer trap designs provide significant improvements in expected power dissipation over the surface trap design in large part due to increased harmonicity. Finally, we consider the fabrication requirements and the path towards the integration of the necessary optical control. This work provides a basis to optimize future trap designs with scalability in mind.
To increase the power of a trapped-ion quantum information processor, the qubit number, gate speed, and gate fidelity must all increase. All three of these parameters are influenced by the trapping field, which, in turn, depends on the electrode geometry. Here, we consider how the electrode geometry affects the following radial trapping parameters: trap height, harmonicity, depth, and trap frequency. We introduce a simple multi-wafer geometry comprising a ground plane above a surface trap and compare the performance of this trap to a surface trap and a multi-wafer trap that is a miniaturized version of a linear Paul trap. We compare the voltage and frequency requirements needed to reach a desired radial trap frequency and find that the two multi-wafer trap designs provide significant improvements in expected power dissipation over the surface trap design in large part due to increased harmonicity. Finally, we consider the fabrication requirements and the path towards the integration of the necessary optical control. This work provides a basis to optimize future trap designs with scalability in mind.
Surface ion traps are a cornerstone technology for scalable quantum information processing, yet their shallow trap depths and limited ion lifetimes remain fundamental engineering bottlenecks. This study presents a systematic experimental and statistical comparison between standard single-wafer surface traps and a novel multi-wafer surface trap architecture in which two parallel wafers with integrated radio-frequency (RF) electrodes are separated by a controllable vertical gap. Seventeen trap configurations were characterized (N = 5 standard, N = 12 multi-wafer), with wafer separations ranging from 50 to 500 µm. Welch’s independent-samples t-tests revealed that the multi-wafer geometry produced a mean trap depth of 23.53 meV compared with 8.50 meV in standard traps (d = 2.71, p < .001), extended ion lifetimes from 120 s to 620.75 s (d = 2.72, p < .001), and reduced anomalous heating rates from 857 to 153 quanta/s (d = −14.75, p < .001). Pearson correlations showed an exceptionally strong positive relationship between wafer separation and trap depth (r = .999, p < .001), and between trap depth and ion lifetime (r = .997, p < .001). A linear regression model explained 99.4% of the variance in ion lifetime from trap depth alone (R² = .995). Qubit coherence time (T₂*) scaled with trap depth, reaching 18.2 ms in the deepest configuration. Results demonstrate that multi-wafer architectures overcome the characteristic depth saturation (∼5.5 meV) of standard designs and produce deeper, more stable, and longer-lived ion traps suitable for scalable quantum computing. Keywords: surface ion trap, multi-wafer architecture, trap depth, ion lifetime, quantum computing, anomalous heating, vertical confinement
Trapped ions in linear Paul traps are largely isolated from interaction with the environment. This property of trapped ions make them a primary choice for quantum technology. \nOver the last decade, trapped atomic ions in linear radio frequency Paul traps have shown to be an important tool to implement quantum algorithms. The scalability of linear ion \ntraps is required to handle large numbers of qubits, in order to implement useful quantum computation. Advance micro-fabrication technology allows the realisation of scalable ion traps. Further developments of micro-trap designs, for the purpose of scalable quantum technology, requires inter-disciplinary investigations of ion traps. Micro-scale ion trap designs typically require a versatile experimental setup. The first part of this thesis describes such an experimental setup including a chip bracket that can host macroscopic ion traps as well as advanced symmetric and asymmetric ion trap chips with up to 90 control electrodes. The system provides versatile optical access for both type of traps and the vacuum chamber is designed in a way so the ion traps can be replaced within a short amount of time. To test the working of the setup, a macroscopic ion trap with an ion-electrode distance of 310±10 μm is used to trap ytterbium ions (Yb+). The trap is characterised by measuring the heating rate, (n•), and spectral noise density SE(ω). A \nphotoionisation technique is used to ionise the different isotopes of Yb in our trap. Isotope selective photoionisation requires exact measurements of 1So↔1P1 transition for the different Yb isotopes. A technique to measure these resonant frequencies is described. \nThis technique works by observing and aligning fluorescence spots and by using this technique, the 1So↔1P1 transition frequencies for stable isotopes of Yb were measured with an accuracy of 60 MHz. These new measured transition frequencies for stable Yb isotopes differ from previously published work by 660 MHz. Furthermore, this technique can also be used to obtain the transition frequencies at different laser-atomic beam angles, typical for non-perpendicular laser-atomic beam angles. The second part of this thesis discusses the optimisation of surface trap geometries as they are being used to implement scalable ion trap designs which consist of a large number of trapping zones. The trap depth in surface traps is low compared to symmetric traps of similar dimensions. How to optimise the trap geometry to achieve maximum trap depth for a given ion height above the trap electrodes, is discussed. Fast and adiabatic ion shuttling operations in one dimension as well as ion separation and recombination processes are important for many quantum information implementations. The maximum speed of separation of trapped ions for adiabatic shuttling operations depends on the secular frequencies, the trapped ion experiences in the process. It will be shown how such ion trap structures have to be designed for fast ion separation process and linear shuttling. Numerical results of adiabatic shuttling operations for trapped ions in such trap structures are also presented.
Among the various physical systems for quantum bit (qubit) implementation, trapped ion has drawn significant attention due to its long coherence time (in the second range) and high gate fidelity (>99.99% for single qubit gate). After years of careful development, the ion trap, from mechanically assembled linear trap to lithography-defined surface electrode ion trap, is compatible with CMOS fabrication, which opens the door for the high-resolution, high-repeatability and large-scale ion trap manufacturing. To date, the number of fully connected ion qubits in state-of-the-art ion trapping devices is ~10. However, to scale close to or even beyond the noisy intermediate-scale quantum regime (NISQ, ~100 ions), some challenges remain. One such challenge is to maintain the delicate control of multiple components over individual ion with increasing ion number. In such context, this thesis is committed to boost the scalability of ion trap by integrating advanced 3D interconnects (e.g., through silicon via) and other functional modules (e.g., silicon photonics and multilayer metallization). 3D interconnects are integrated in the half space underneath surface electrode, to replace conventional wire bonding that extends out of the surface. Silicon photonics (grating coupler and waveguide) in place of bulk optics and lenses are used for on-chip light routing and emission. Multilayer metallization is used to maintain the overall RF performance and enable high-density interconnection where necessary. Firstly, surface electrode ion traps on different substrates (namely high resistivity silicon, silicon with grounding plane and glass) are designed and fabricated. Standard CMOS back-end-of-line fabrication process on 12-inch wafer platform is employed. The electrical performances of different traps are compared in terms of leakage current (I-V), parasitic capacitance (C-V), on-chip RF loss (S-parameter) and post-packaging resonance. Though the leakage (at the order of 10-8 A) between neighboring electrodes is relatively high, ion trap on glass substrate demonstrates extremely small capacitance (<1 pF) and low RF loss (insertion loss of <0.05 dB at RF frequency of 50 MHz), as compared to the silicon counterparts. This is mainly due to excellent insulation property of glass. Following that, ion trapping test is performed on the glass trap and ions are successfully confined with an averaged lifetime of ~30 minutes (compatible with the 10-11 mbar vacuum level (10-13 Pa)). To simultaneously leverage the dielectric property of glass and the microfabrication compatibility of silicon, the integration of silicon ion trap and glass interposer is performed, between which TSV is used to build the vertical interconnection. Due to the incorporation of TSV, the original wire bonding pads as well as the connection circuits on the surface electrodes can be eliminated. As a result, the form factor of TSV integrated trap is reduced by ~10 times. Correspondingly, the parasitic capacitance between neighboring electrodes is reduced from >24 pF to 3 pF. Similarly, the insertion loss of TSV integrated trap drops to 0.11 dB, in sharp comparison to the previous traps on silicon substrates (up to 2.4 dB). Analytical models are built to respectively characterize the electrode capacitance and overall power loss, and a good agreement is achieved between the model and the measurement result. In addition, since TSV is located in the half space underneath the surface electrodes, the electrodes geometry design is enabled with high flexibility. Meanwhile, the laser obstruction issue due to the stick-out bonding wires has been resolved. In terms of the ion trapping performance, both the heating rate (17 quanta/ms for an axial frequency of 300 kHz) and the lifetime (~30 minutes) of TSV trap are comparable with non-cryogenic traps of similar dimensions. Moreover, a customized CPGA with patterned redistribution layer is used to locate TSV integrated trap directly in the absence of glass interposer, facilitating high-efficiency thermal management and upgrading the packaging flexibility. At the next stage, the co-integration of other functional modules such as silicon photonics and multilayer metallization with TSV trap is investigated. In silicon photonics module, waveguide and grating coupler are on-chip introduced in place of bulk optics to achieve localized light routing and emission. In multilayer metallization module, as a first step, a grounding plane is incorporated into TSV trap to shield the silicon substrate from RF signal, in which specific windows are patterned onto the plane to accommodate TSV and allow the transmission of lights. The compatibility between TSV/multilayer metallization and waveguide/grating coupler for electrical and optical (E/O) signal routing is demonstrated. The preliminary test result based on wafer frontside shows that a ~40% capacitance reduction is achieved, and the insertion loss further drops to 0.06 dB, close to the performance of glass trap. In addition, the simulation results on photonics components indicate that an overall coupling efficiency of <30 dB is obtained from the input fiber to the ion through the photonics circuit. However, the measured power loss for light with wavelength of 1092 nm is as high as 50 dB. The deviation between the simulation and measurement is largely due to the fabrication imperfection and the resultant sloped grating coupler profile. This thesis focuses on the scalability enhancement of ion trap by integrating TSV, silicon photonics and multilayer metallization into conventional ion trap. The results are promising and pave the way for the future large scale quantum computing based on trapped ion.
The majority of microfabricated ion traps in use for quantum information processing are of the 2D 'surface-electrode' type or of the 3D 'wafer' type. Surface-electrode traps greatly simplify fabrication and hold the promise of allowing trapped-ion quantum computers to scale via standard semiconductor industry fabrication techniques. However, their geometry constrains them to having much lower trapping efficiency, depth, and harmonicity compared to 3D geometries. Conversely 3D geometries offer superior trap performance but fabrication is more complex, limiting potential to scale. We describe new 'trench' geometries that exist in the design space between these two paradigms. They still allow for a simple, planar electrode layer but with much more favourable trapping properties. We propose such traps could be 3D-printed over a 2D wafer with microfabricated components already integrated into it, thus retaining all the integration techniques and scaling advantages of surface-electrode traps. As a proof of principle we use 2-photon direct laser writing lithography to print the required electrode structures with the proposed geometry.
Trapped ions within Paul traps have shown to be a promising architecture in the realisation of a quantum information processor together with the ability of providing quantum simulations. Linear Paul traps have demonstrated long coherence times with ions being well isolated from the environment, single and multi-qubit gates and the high fidelity detection of states. The scalability to large number of qubits, incorporating all the previous achievements requires an array of linear ion traps. Microfabrication techniques allow for fabrication and micron level accuracy of the trap electrode dimensions through photolithography techniques. The first part of this thesis presents the experiential setup and trapping of Yb+ ions needed to test large ion trap arrays. This include vacuum systems that can host advanced symmetric and asymmetric ion traps with up to 90 static voltage control electrodes. Demonstration of a single trapped Yb+ ion within a two-layer macroscopic ion trap is presented. with an ion-electrode distance of 310(10) µm. The anomalous heating rate and spectral noise density of the trap was measured, a main form of decoherence within ion traps. The second half of this thesis presents the design and fabrication of multi-layer asymmetric ion traps. This allows for isolated electrodes that cannot be accessed via surface pathways, allowing for higher density of electrodes as well as creating novel trap designs that allow for the potential of quantum simulations to be demonstrated. These include two-dimensional lattices and ring trap designs in which the isolated electrodes provide more control in the ion position. For the microfabrication of these traps I present a novel high-aspect ratio electroplated electrode design that provides shielding of the dielectric layer. This provides a means to mitigate stray electric field due to charge build up on the dielectric surfaces. Electrical testing of the trap structures was performed to test bulk breakdown and surface flashover of the ion trap architectures. Results showed sufficient isolation between electrodes for both radio frequency and static breakdown. Surface flashover voltage measurements over the dielectric layer showed an improvement of more than double over previous results using a new fabrication technique. This will allow for more powerful ion trap chips needed for the next generation of microfabricated ion trap arrays for scalable quantum technologies.
Trapped-ion applications, such as in quantum information, precision measurements, optical clocks, and mass spectrometry, rely on specialized high-performance ion traps. The latter applications typically employ traditional machining to customize macroscopic 3D Paul traps, while quantum information processing experiments usually rely on photo-lithographic techniques to miniaturize the traps and meet scalability requirements. Using photolithography, however, it is challenging to fabricate the complex three-dimensional electrode structures required for optimal confinement. Here we address these limitations by adopting a high-resolution 3D printing technology based on two-photon polymerization supporting fabrication of large arrays of high-performance miniaturized 3D traps. We show that 3D-printed ion traps combine the advantages of traditionally machined 3D traps with the miniaturization provided by photolithography by confining single calcium ions in a small 3D-printed ion trap with radial trap frequencies ranging from 2 MHz to 24 MHz. The tight confinement eases ion cooling requirements and allows us to demonstrate high-fidelity coherent operations on an optical qubit after only Doppler cooling. With 3D printing technology, the design freedom is drastically expanded without sacrificing scalability and precision so that ion trap geometries can be optimized for higher performance and better functionality.