Surface ion traps are a cornerstone technology for scalable quantum information processing, yet their shallow trap depths and limited ion lifetimes remain fundamental engineering bottlenecks. This study presents a systematic experimental and statistical comparison between standard single-wafer surface traps and a novel multi-wafer surface trap architecture in which two parallel wafers with integrated radio-frequency (RF) electrodes are separated by a controllable vertical gap. Seventeen trap configurations were characterized (N = 5 standard, N = 12 multi-wafer), with wafer separations ranging from 50 to 500 µm. Welch’s independent-samples t-tests revealed that the multi-wafer geometry produced a mean trap depth of 23.53 meV compared with 8.50 meV in standard traps (d = 2.71, p < .001), extended ion lifetimes from 120 s to 620.75 s (d = 2.72, p < .001), and reduced anomalous heating rates from 857 to 153 quanta/s (d = −14.75, p < .001). Pearson correlations showed an exceptionally strong positive relationship between wafer separation and trap depth (r = .999, p < .001), and between trap depth and ion lifetime (r = .997, p < .001). A linear regression model explained 99.4% of the variance in ion lifetime from trap depth alone (R² = .995). Qubit coherence time (T₂*) scaled with trap depth, reaching 18.2 ms in the deepest configuration. Results demonstrate that multi-wafer architectures overcome the characteristic depth saturation (∼5.5 meV) of standard designs and produce deeper, more stable, and longer-lived ion traps suitable for scalable quantum computing. Keywords: surface ion trap, multi-wafer architecture, trap depth, ion lifetime, quantum computing, anomalous heating, vertical confinement
Surface ion traps are a cornerstone technology for scalable quantum information processing, yet their shallow trap depths and limited ion lifetimes remain fundamental engineering bottlenecks. This study presents a systematic experimental and statistical comparison between standard single-wafer surface traps and a novel multi-wafer surface trap architecture in which two parallel wafers with integrated radio-frequency (RF) electrodes are separated by a controllable vertical gap. Seventeen trap configurations were characterized (N = 5 standard, N = 12 multi-wafer), with wafer separations ranging from 50 to 500 µm. Welch’s independent-samples t-tests revealed that the multi-wafer geometry produced a mean trap depth of 23.53 meV compared with 8.50 meV in standard traps (d = 2.71, p < .001), extended ion lifetimes from 120 s to 620.75 s (d = 2.72, p < .001), and reduced anomalous heating rates from 857 to 153 quanta/s (d = −14.75, p < .001). Pearson correlations showed an exceptionally strong positive relationship between wafer separation and trap depth (r = .999, p < .001), and between trap depth and ion lifetime (r = .997, p < .001). A linear regression model explained 99.4% of the variance in ion lifetime from trap depth alone (R² = .995). Qubit coherence time (T₂*) scaled with trap depth, reaching 18.2 ms in the deepest configuration. Results demonstrate that multi-wafer architectures overcome the characteristic depth saturation (∼5.5 meV) of standard designs and produce deeper, more stable, and longer-lived ion traps suitable for scalable quantum computing. Keywords: surface ion trap, multi-wafer architecture, trap depth, ion lifetime, quantum computing, anomalous heating, vertical confinement
Among the various physical systems for quantum bit (qubit) implementation, trapped ion has drawn significant attention due to its long coherence time (in the second range) and high gate fidelity (>99.99% for single qubit gate). After years of careful development, the ion trap, from mechanically assembled linear trap to lithography-defined surface electrode ion trap, is compatible with CMOS fabrication, which opens the door for the high-resolution, high-repeatability and large-scale ion trap manufacturing. To date, the number of fully connected ion qubits in state-of-the-art ion trapping devices is ~10. However, to scale close to or even beyond the noisy intermediate-scale quantum regime (NISQ, ~100 ions), some challenges remain. One such challenge is to maintain the delicate control of multiple components over individual ion with increasing ion number. In such context, this thesis is committed to boost the scalability of ion trap by integrating advanced 3D interconnects (e.g., through silicon via) and other functional modules (e.g., silicon photonics and multilayer metallization). 3D interconnects are integrated in the half space underneath surface electrode, to replace conventional wire bonding that extends out of the surface. Silicon photonics (grating coupler and waveguide) in place of bulk optics and lenses are used for on-chip light routing and emission. Multilayer metallization is used to maintain the overall RF performance and enable high-density interconnection where necessary. Firstly, surface electrode ion traps on different substrates (namely high resistivity silicon, silicon with grounding plane and glass) are designed and fabricated. Standard CMOS back-end-of-line fabrication process on 12-inch wafer platform is employed. The electrical performances of different traps are compared in terms of leakage current (I-V), parasitic capacitance (C-V), on-chip RF loss (S-parameter) and post-packaging resonance. Though the leakage (at the order of 10-8 A) between neighboring electrodes is relatively high, ion trap on glass substrate demonstrates extremely small capacitance (<1 pF) and low RF loss (insertion loss of <0.05 dB at RF frequency of 50 MHz), as compared to the silicon counterparts. This is mainly due to excellent insulation property of glass. Following that, ion trapping test is performed on the glass trap and ions are successfully confined with an averaged lifetime of ~30 minutes (compatible with the 10-11 mbar vacuum level (10-13 Pa)). To simultaneously leverage the dielectric property of glass and the microfabrication compatibility of silicon, the integration of silicon ion trap and glass interposer is performed, between which TSV is used to build the vertical interconnection. Due to the incorporation of TSV, the original wire bonding pads as well as the connection circuits on the surface electrodes can be eliminated. As a result, the form factor of TSV integrated trap is reduced by ~10 times. Correspondingly, the parasitic capacitance between neighboring electrodes is reduced from >24 pF to 3 pF. Similarly, the insertion loss of TSV integrated trap drops to 0.11 dB, in sharp comparison to the previous traps on silicon substrates (up to 2.4 dB). Analytical models are built to respectively characterize the electrode capacitance and overall power loss, and a good agreement is achieved between the model and the measurement result. In addition, since TSV is located in the half space underneath the surface electrodes, the electrodes geometry design is enabled with high flexibility. Meanwhile, the laser obstruction issue due to the stick-out bonding wires has been resolved. In terms of the ion trapping performance, both the heating rate (17 quanta/ms for an axial frequency of 300 kHz) and the lifetime (~30 minutes) of TSV trap are comparable with non-cryogenic traps of similar dimensions. Moreover, a customized CPGA with patterned redistribution layer is used to locate TSV integrated trap directly in the absence of glass interposer, facilitating high-efficiency thermal management and upgrading the packaging flexibility. At the next stage, the co-integration of other functional modules such as silicon photonics and multilayer metallization with TSV trap is investigated. In silicon photonics module, waveguide and grating coupler are on-chip introduced in place of bulk optics to achieve localized light routing and emission. In multilayer metallization module, as a first step, a grounding plane is incorporated into TSV trap to shield the silicon substrate from RF signal, in which specific windows are patterned onto the plane to accommodate TSV and allow the transmission of lights. The compatibility between TSV/multilayer metallization and waveguide/grating coupler for electrical and optical (E/O) signal routing is demonstrated. The preliminary test result based on wafer frontside shows that a ~40% capacitance reduction is achieved, and the insertion loss further drops to 0.06 dB, close to the performance of glass trap. In addition, the simulation results on photonics components indicate that an overall coupling efficiency of <30 dB is obtained from the input fiber to the ion through the photonics circuit. However, the measured power loss for light with wavelength of 1092 nm is as high as 50 dB. The deviation between the simulation and measurement is largely due to the fabrication imperfection and the resultant sloped grating coupler profile. This thesis focuses on the scalability enhancement of ion trap by integrating TSV, silicon photonics and multilayer metallization into conventional ion trap. The results are promising and pave the way for the future large scale quantum computing based on trapped ion.
To increase the power of a trapped-ion quantum information processor, the qubit number, gate speed, and gate fidelity must all increase. All three of these parameters are influenced by the trapping field, which, in turn, depends on the electrode geometry. Here, we consider how the electrode geometry affects the following radial trapping parameters: trap height, harmonicity, depth, and trap frequency. We introduce a simple multi-wafer geometry comprising a ground plane above a surface trap and compare the performance of this trap to a surface trap and a multi-wafer trap that is a miniaturized version of a linear Paul trap. We compare the voltage and frequency requirements needed to reach a desired radial trap frequency and find that the two multi-wafer trap designs provide significant improvements in expected power dissipation over the surface trap design in large part due to increased harmonicity. Finally, we consider the fabrication requirements and the path towards the integration of the necessary optical control. This work provides a basis to optimize future trap designs with scalability in mind.
Abstract Scaling trapped-ion quantum computing will require robust trapping of at least hundreds of ions over long periods, while increasing the complexity and functionality of the trap itself. Symmetric three-dimensional (3D) structures enable high trap depth, but microfabrication techniques are generally better suited to planar structures that produce less ideal conditions for trapping. We present an ion trap fabricated on stacked eight-inch wafers in a large-scale micro-electro-mechanical system microfabrication process that provides reproducible traps at a large volume. Electrodes are patterned on the surfaces of two opposing wafers bonded to a spacer, forming a 3D structure with 2.5 μm standard deviation in alignment across the stack. We implement a design achieving a trap depth of 1 eV for a 40Ca+ ion held at 200 μm from either electrode plane. We characterize traps, achieving measurement agreement with simulations to within ±5% for mode frequencies spanning 0.6–3.8 MHz, and evaluate stray electric field across multiple trapping sites. We measure motional heating rates over an extensive range of trap frequencies, and temperatures, observing 40 phonons/s at 1 MHz and 185 K. This fabrication method provides a highly scalable approach for producing a new generation of 3D ion traps.
In this study, we report about the design, fabrication, and operation of a Cu-filled through-silicon via (TSV)-integrated ion trap. TSVs are placed directly underneath electrodes as vertical interconnections between an ion trap and a glass interposer, facilitating the arbitrary geometry design with increasing electrode numbers and evolving complexity. The integration of TSVs reduces the form factor of the ion trap by more than 80%, minimizing parasitic capacitance from 32 ± 2 to 3 ± 0.2 pF. A low RF dissipation is achieved in spite of the absence of the ground screening layer. The entire fabrication process is on a 12-in. wafer and compatible with the established CMOS back end process. We demonstrate the basic functionality of the trap by loading and laser-cooling single 88Sr+ ions. It is found that both the heating rate (17 quanta/ms for an axial frequency of 300 kHz) and lifetime (∼30 min) are comparable with traps of similar dimensions. This work pioneers the development of TSV-integrated ion traps, enriching the toolbox for scalable quantum computing.
Surface ion traps with two-dimensional layouts of trapping regions are natural architectures for storing large numbers of ions and supporting the connectivity needed to implement quantum algorithms. Many of the components and operations needed to fully exploit this architecture have already been demonstrated, including operation at cryogenic temperatures with low heating, low excitation transport, and ion control and detection with integrated photonics. Here we demonstrate a trap that addresses the scaling challenge of increasing power dissipation as the RF electrode increases in size. By raising the RF electrode and removing most of the insulating dielectric layer below it we reduce both ohmic and dielectric power dissipation. We also measure heating rates across a range of motional frequencies and for different voltage sources in a trap with a raised RF electrode but solid dielectric.
In this study, we report the first Cu-filled through silicon via (TSV) integrated ion trap. TSVs are placed directly underneath electrodes as vertical interconnections between ion trap and a glass interposer, facilitating the arbitrary geometry design with increasing electrodes numbers and evolving complexity. The integration of TSVs reduces the form factor of ion trap by more than 80%, minimizing parasitic capacitance from 32 to 3 pF. A low RF dissipation is achieved in spite of the absence of ground screening layer. The entire fabrication process is on 12-inch wafer and compatible with established CMOS back end process. We demonstrate the basic functionality of the trap by loading and laser-cooling single 88Sr+ ions. It is found that both heating rate (17 quanta/ms for an axial frequency of 300 kHz) and lifetime (~30 minutes) are comparable with traps of similar dimensions. This work pioneers the development of TSV-integrated ion traps, enriching the toolbox for scalable quantum computing.