High-Throuput Bit-Slice Multipliers Using SFQ Circuits

Yoshitaka Takahashi, Moriya Masataka, Shimada Hiroshi +2 more

Sasan Razmkhah, Ali Bozbey, Pascal Febvre

Yoshinao Mizugaki, Jun Saito, Masataka Moriya +1 more

Guang-Ming Tang, Kazuyoshi Takagi, Naofumi Takagi

A 4-bit bit-slice multiplier for a 32-bit rapid single-flux-quantum (RSFQ) microprocessor is proposed. It carries out both signed and unsigned integer multiplication. A fully pipelined RSFQ logic design of the multiplier using concurrent flow clocking consists of 33 stages and 17,551 Josephson junctions. The bit-slice approach simplifies the circuit complexity and reduces the hardware cost. For verification, an 8×8-bit 4-bit bit-slice multiplier based on the proposed algorithm has been designed and simulated using AIST 10-kA/cm21.0-μm fabrication technology. The simulation result shows correct operation at 62.5 GHz.

Ikki Nagaoka, Masamitsu Tanaka, Kyosuke Sano +3 more

賢介 高田, 雄飛 早川, 雅光 田中 +1 more

A large number of researches on designing digital circuits by using SFQ logic circuits have been undertaken extensively. We have been developing SFQ microprocessors. In our demonstrated SFQ microprocessors, bit serial architectures were used. In order to increase the performance of the microprocessors, we have designed a bit-slice adder toward introduction of a bit-slice architecture. In this paper, we present a bit-parallel, serial, and slice architectures, and we compare and evaluate the operating times and circuit sizes of the adders based on these architectures. We also report design of a 2-bit bit-slice adder using AIST 10 kA/cm^2 niobium advanced process, and demonstration of its high-speed operation.