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IEICE Technical Report; IEICE Tech. Rep.

10kA/cm^2プロセスを用いた2-bitビットスライス・アダーの設計と評価

賢介 高田, 雄飛 早川, 雅光 田中, 朗 藤巻

Published Jul 15, 2013• 0 citations
OpenAlex

Abstract

A large number of researches on designing digital circuits by using SFQ logic circuits have been undertaken extensively. We have been developing SFQ microprocessors. In our demonstrated SFQ microprocessors, bit serial architectures were used. In order to increase the performance of the microprocessors, we have designed a bit-slice adder toward introduction of a bit-slice architecture. In this paper, we present a bit-parallel, serial, and slice architectures, and we compare and evaluate the operating times and circuit sizes of the adders based on these architectures. We also report design of a 2-bit bit-slice adder using AIST 10 kA/cm^2 niobium advanced process, and demonstration of its high-speed operation.

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A large number of researches on designing digital circuits by using SFQ logic circuits have been undertaken extensively. We have been developing SFQ microprocessors. In our demonstrated SFQ microprocessors, bit serial architectures were used. In order to increase the performance of the microprocessors, we have designed a bit-slice adder toward introduction of a bit-slice architecture. In this paper, we present a bit-parallel, serial, and slice architectures, and we compare and evaluate the operating times and circuit sizes of the adders based on these architectures. We also report design of a 2-bit bit-slice adder using AIST 10 kA/cm^2 niobium advanced process, and demonstration of its high-speed operation.
We propose an algorithm of digit-serial adders using single-flux-quantum (SFQ) circuits. The proposed digit-serial adder adapts the carry look-ahead (CLA) adder architecture to generate carry signals, which are generated from the digit-serial data and fed back internally to the following digit-serial data to increase the throughput of the calculation. We have designed and implemented a 4-bit digit-serial adder using the SRL 2.5kA/cm2 niobium standard process to demonstrate its high-speed operation. The total number of Josephson junctions is 2316. We have successfully tested full operations of the 4-bit digit-serial adder with a bias margin of ± 15% at 25GHz. Its maximum operation frequency was 30GHz.
100-GHz Single-Flux-Quantum Bit-Serial Adder Based on 10-kA/cm2{\rm kA/cm}^{2}kA/cm2 Niobium Process
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We have been developing a large-scale reconfigurable data-path (LSRDP) based on single-flux-quantum (SFQ) circuits to establish a fundamental technology for future high-performance computing systems. The SFQ floating-point adder (FPA) is one of the principal and most complicated circuit blocks in an LSRDP. In this study, we designed and implemented component circuits of an SFQ bit-serial half-precision FPA using the cell library for a 10-kA/cm2Nb process and performed on-chip high-speed tests. We demonstrated correct operation of the four-bit shifter for the significand at the clock frequencies of up to 76 GHz. The dependence of the measured DC bias margin on the operating frequency agrees reasonably well with the margin calculated using a digital simulation. The operation of the normalizer for the significand has been also confirmed at low speeds.
We describe the development of single-flux-quantum (SFQ) microprocessors and the related technologies such as designing, circuit architecture, microarchitecture, etc. Since the microprocessors studied here aim for a general-purpose computing system, we employ the complexity-reduced (CORE) architecture in which the high-speed nature of the SFQ circuits is used not for increasing processor performance but for reducing the circuit complexity. The bit-serial processing is the most suitable way to realize the CORE architecture. We assembled all the best technologies concerning SFQ integrated circuits and designed the SFQ microprocessors, CORE1α, CORE1β, and CORE1γ. The CORE1β was made up of about 11000 Josephson junctions and successfully demonstrated. The peak performance reached 1400 million operations per second with a power consumption of 3.4mW. We showed that the SFQ microprocessors had an advantage in a performance density to semiconductor's ones, which lead to the potential for constructing a high performance SFQ-circuit-based computing system.
Design and Implementation of a Pipelined Bit-Serial SFQ Microprocessor, CORE1β{\rm CORE}1\betaCORE1β
A pipelined 8-bit-serial single-flux-quantum (SFQ) microprocessor, called CORE1beta, was designed and tested. The CORE1beta has two cascaded arithmetic logic units (ALUs) based on forwarding architecture, which can perform two register operations from one instruction. Pipelining is also extensively adopted to enhance the performance. A new design method, known as one-hot encoding, has been introduced into the design of the control circuit. The 4-stage-pipelined SFQ microprocessors, CORE1beta8, have been implemented using the CONNECT cell library and the SRL 2.5 kA/cm2Nb process. The frequency for the instruction fetch is 25 GHz, and 20 GHz for the bit-serial data operation. The peak performance and the power consumption of the CORE1beta8 are estimated to be 1400 MOPS (million instructions per second) and 3.4 mW, respectively. We have experimentally demonstrated 4-stage pipelining and all functionalities of the CORE1beta8 microprocessors by on-chip high-speed tests.
We are developing a large-scale reconfigurable data-path (LSRDP) based on single-flux-quantum (SFQ) circuits to establish a fundamental technology for future high-performance computing systems. In the LSRDP, an SFQ floating-point adder (FPA) is one of the main and most complicated circuit blocks. In our previous study, we implemented an SFQ half-precision (16-bit) bit-serial FPA using the ISTEC 2.5 kA/cm2standard process, and demonstrated the correct operations at 24 GHz by on-chip high-speed tests. In this study, we designed and implemented an SFQ half-precision bit-serial FPA using a cell library for the AIST 10 kA/cm2Nb nine-metal-layer process (ADP2), and carried out on-chip high speed tests. The designed FPA contains 9661 Josephson junctions and occupies a circuit area of 12.95 mm2. Its target operation frequency is 50 GHz. We have demonstrated the correct operation of the FPA at the maximum frequency of 62 GHz although there is a functional error in the design. The measured DC bias margin ranges from 102% to 108% at 50 GHz operation. The total power consumption is measured to be 2.9 mW.