Among advanced paradigms in the physics of computing, adiabatic quantum-flux-parametron (AQFP) logic is interesting, in that it can easily introduce stochastic processes by exploiting naturally occurring thermal fluctuations. This study proposes using AQFP logic to implement stochastic-local-search solvers. Experiments show that AQFP circuits can find solutions to simple logical constraint-satisfaction problems when moderate thermal fluctuations are applied. This result indicates the possibility of superconducting digital circuits dedicated to solving combinatorial optimization problems.
Among advanced paradigms in the physics of computing, adiabatic quantum-flux-parametron (AQFP) logic is interesting, in that it can easily introduce stochastic processes by exploiting naturally occurring thermal fluctuations. This study proposes using AQFP logic to implement stochastic-local-search solvers. Experiments show that AQFP circuits can find solutions to simple logical constraint-satisfaction problems when moderate thermal fluctuations are applied. This result indicates the possibility of superconducting digital circuits dedicated to solving combinatorial optimization problems.
Abstract Adiabatic quantum-flux-parametron (AQFP) logic is an energy-efficient superconductor logic with zero static power and very small dynamic power due to adiabatic switching operations. In order to build large-scale digital circuits, we built AQFP logic cells using superconductor magnetic shields, which are necessary in order to avoid unwanted magnetic couplings between the cells and excitation currents. In preliminary experimental tests, we confirmed that the unwanted coupling became negligibly small thanks to the superconductor shields. As a demonstration, we designed a four-to-one multiplexor and a 16-junction full adder using the shielded logic cells. In both circuits, we confirmed correct logic operations with wide operation margins of excitation currents. These results indicate that large-scale AQFP digital circuits can be realized using the shielded logic cells.
Abstract Superconductor logic families can operate with small power dissipation and are thus suitable as building blocks for various computing systems. In some applications, superconductor logic circuits should be designed using Josephson junctions with low I c values ( I c : critical current). For instance, lowering I c values enables qubit interface circuits to operate with very small power dissipation at ~10 mK and stochastic electronics to easily induce stochastic operations. In this study, we develop the AIST 1 kA cm −2 Nb planarized process (1KP) with a minimum critical current of 10 µA, dedicated to the design of qubit interface circuits and stochastic electronics. We also develop rapid single-flux-quantum (RSFQ) and adiabatic quantum-flux-parametron (AQFP) cell libraries using the 1KP. The power dissipation of RSFQ logic using the 1KP can be reduced to 3.2% of that for conventional RSFQ logic by reducing both I c values and a bias voltage. Furthermore, the amount of supply currents for AQFP circuits using the 1KP can be reduced to ~40% of that for conventional AQFP circuits due to a large mutual inductance between AQFP gates and excitation lines, which results from a reduction in I c and an increase in inductances. We demonstrate RSFQ and AQFP circuits fabricated by the 1KP at 4.2 K. These results indicate that RSFQ and AQFP circuits using the 1KP have the potential to be used for the design of qubit interface circuits and stochastic electronics.
Superconductor/ferromagnet/superconductor Josephson junctions across which the phases of superconducting order parameters are shifted by π in the ground state are called π Josephson junctions (π-JJs). Recently, several groups have established the fabrication technology of π-JJs so that superconductor logic families exploit π-JJs to improve circuit performance. In this paper, we investigate the advantages of π-JJs in adiabatic quantum-flux-parametron (AQFP) logic, which is an adiabatic superconductor logic based on the quantum-flux-parametron. First, we show that AQFP logic with π-JJs (π-AQFP) can operate using only π-JJs and can be powered and clocked in the same way as the conventional AQFP logic. Then, we show that π-AQFP logic can realize inverters without using signal transformers, which generally occupy a large area in AQFP gates and are difficult to miniaturize. We demonstrate π-AQFP inverters using numerical simulation to establish that π-AQFP logic operates adiabatically and robustly. Our results show that π-JJs can be easily incorporated into AQFP logic and enhance the circuit density of AQFP logic.
Adiabatic quantum-flux-parametron (AQFP) superconductor logic is a proven energy-efficient digital technology for various applications. To address the scalability challenges of this technology, we investigated AQFP shift registers with the AQFP footprint area reduced by 25% with respect to prior work and with the >2× denser overall circuit designs obtained by eliminating the previously used free space between the AQFPs. We also investigated AQFP cells with different designs of flux trapping moats in the superconducting ground plane as well as compact AQFP cells that took advantage of the smaller feature sizes available in the new fabrication process, SFQ5ee+, at MIT Lincoln Laboratory (MIT LL). This new process features nine planarized Nb layers with a 0.25 μm minimum linewidth. The fabricated circuits were tested in a liquid He immersion probe and a commercial closed-cycle cryocooler using a controlled cooling rate through the superconducting critical temperature,Tc. Using multiple thermal cycles, we investigated flux trapping in the dense AQFP shift registers as well as in the registers using the old (sparse) AQFP designs at two levels of the residual magnetic field, about 0.53 μT and about 1.2 μT. The sparse designs demonstrated 95% to almost 100% probability of operation after the cooldown and very wide operation margins, although the flux trapping probability was increasing with circuit complexities. The margins were similarly wide in the newer dense designs, but flux trapping probability that rendered the registers nonoperational was significantly, by an order of magnitude, higher in these denser circuits and was also very sensitive to the moats' shape and location. Our findings indicate that AQFP circuits are amendable to increasing the scale of integration and further densification, but a careful moat design and optimization are required to reduce flux trapping effects in the dense AQFP circuits.
We have been developing the adiabatic quantum-flux-parametron (AQFP), which is an ultra-low-power superconductor logic family. To date, somewhat large AQFP circuits, such as a 4-bit microprocessor and an 8-bit adder, have been demonstrated. To design much larger devices, space-efficient logic circuits are needed. Therefore, in a previous study, we proposed the directly coupled quantum-flux-parametron (DQFP). DQFP circuits propagate data via a direct connection, whereas AQFP circuits propagate data via transformers, which can occupy a large part of the gate area. Thus, DQFP circuits are more space-efficient than AQFP circuits. In this study, we optimized the circuit parameters for DQFP logic cells using numerical simulations from the viewpoint of excitation current margins, component parameter margins, and energy dissipation. We also designed the physical layout of the optimized DQFP cells, fabricated chips, and demonstrated basic DQFP circuits with the optimized cells.
Abstract We present a comprehensive overview of a design methodology and environment that we developed to enable the implementation of microprocessors and other complex logic circuits using the adiabatic quantum-flux-parametron (AQFP) superconductor logic family. The design environment is catered for both the AIST 10 kA cm −2 Nb high-speed standard process as well as the AIST 2.5 kA cm −2 Nb standard process (STP2). We detail each aspect of the design flow, highlighting improvements in cell design, and new developments in circuit retiming to reduce the number of synchronizing buffers in the circuit datapath. With retiming, we expect a 14–37% reduction in the overall Josephson junction (JJ) count for some benchmarks. Finally, we show the successful experimental demonstration of an arithmetic logic unit and data shifter for an AQFP microprocessor using the established methodology and environment. The demonstrated circuits show full functionality and wide excitation current margins of nearly ±30%, which corresponds well with simulation results.