Superconductor/ferromagnet/superconductor Josephson junctions across which the phases of superconducting order parameters are shifted by π in the ground state are called π Josephson junctions (π-JJs). Recently, several groups have established the fabrication technology of π-JJs so that superconductor logic families exploit π-JJs to improve circuit performance. In this paper, we investigate the advantages of π-JJs in adiabatic quantum-flux-parametron (AQFP) logic, which is an adiabatic superconductor logic based on the quantum-flux-parametron. First, we show that AQFP logic with π-JJs (π-AQFP) can operate using only π-JJs and can be powered and clocked in the same way as the conventional AQFP logic. Then, we show that π-AQFP logic can realize inverters without using signal transformers, which generally occupy a large area in AQFP gates and are difficult to miniaturize. We demonstrate π-AQFP inverters using numerical simulation to establish that π-AQFP logic operates adiabatically and robustly. Our results show that π-JJs can be easily incorporated into AQFP logic and enhance the circuit density of AQFP logic.
Superconductor/ferromagnet/superconductor Josephson junctions across which the phases of superconducting order parameters are shifted by π in the ground state are called π Josephson junctions (π-JJs). Recently, several groups have established the fabrication technology of π-JJs so that superconductor logic families exploit π-JJs to improve circuit performance. In this paper, we investigate the advantages of π-JJs in adiabatic quantum-flux-parametron (AQFP) logic, which is an adiabatic superconductor logic based on the quantum-flux-parametron. First, we show that AQFP logic with π-JJs (π-AQFP) can operate using only π-JJs and can be powered and clocked in the same way as the conventional AQFP logic. Then, we show that π-AQFP logic can realize inverters without using signal transformers, which generally occupy a large area in AQFP gates and are difficult to miniaturize. We demonstrate π-AQFP inverters using numerical simulation to establish that π-AQFP logic operates adiabatically and robustly. Our results show that π-JJs can be easily incorporated into AQFP logic and enhance the circuit density of AQFP logic.
Each superconductor logic family has distinct features and advantages. For instance, adiabatic quantum-flux-parametron (AQFP) circuits operate with very high energy efficiency, and rapid single-flux-quantum (RSFQ) circuits operate at very high clock frequencies. To build a hybrid system that combines the above advantages, we propose a compact interface between AQFP and RSFQ circuits that converts current signals in AQFP logic into flux signals in RSFQ logic using a non-adiabatic quantum-flux-parametron gate. Compared to a previously proposed AQFP/RSFQ interface, the proposed interface has far fewer Josephson junctions (4 vs. 11). We optimize the circuit parameters of the AQFP/RSFQ interface and demonstrate the interface at low speed as proof of concept. Furthermore, we demonstrate data propagation between AQFP circuits along a long passive transmission line via the AQFP/RSFQ interface at low speed to show that the AQFP/RSFQ interface can alleviate the interconnect length limit in AQFP circuits.
Abstract Adiabatic superconductor logic (ASL) families are energy-efficient because they can operate with a switching energy much less than the I cΦ0 product, where I c is the critical current for Josephson junctions, Φ0 is the flux quantum, and I cΦ0 is generally on the order of 10–19 J. A switching energy of 0.03I cΦ0 has been demonstrated by adiabatic quantum-flux-parametron (AQFP) logic, which indicates the possibility of extremely energy-efficient digital circuits using ASL. ASL uses signal transformers to propagate and invert the signal current; otherwise, it is difficult to design inverters. However, signal transformers are generally difficult to miniaturize. Therefore, to realize high-density and energy-efficient superconductor circuits, ASL that does not use signal transformers is required. In this paper, we propose ASL without signal transformers, which we call directly coupled quantum-flux-parametron (DQFP). DQFP logic is based on AQFP, but it can invert signal current without using signal transformers. We conducted numerical simulation of a DQFP inverter chain to show that DQFP logic can invert signal current without signal transformers, and that DQFP logic can operate adiabatically. Then, we designed and fabricated basic DQFP circuits, such as an inverter chain and a full adder. All the circuits were found to have wide operating margins. Our results indicate that DQFP logic is suitable for high-density and energy-efficient superconductor circuits.
Adiabatic quantum flux parametron (AQFP) is a very energy-efficient superconductor logic. In AQFP logic, dynamic energy dissipation can be drastically reduced due to adiabatic switching operations using ac excitation currents. In the present study, we evaluated circuit yields using a large-scale AQFP circuit composed of as many as 10,000 AQFP gates with approximately 20,000 Josephson junctions. We measured eleven chips from four wafers and obtained circuit yields of 48% for 1,000-gate circuits and 22% for 10,000-gate circuits, respectively. In all the circuits, which worked correctly, the margins of excitation currents were as wide as approximately ±20%.
Adiabatic quantum flux parametron (AQFP) gate is a promising approach to scale up the cryogenic microwave electronics for superconducting qubit multiplexed control. However, the performance of these circuits depends on the quality of the Josephson junctions which are ideally superconductor-insulator-superconductor (SIS) type following the ideal sinusoidal relation between current and quantum phase. We demonstrate how the non-sinusoidal current-phase relation in Superconductor-Normal metal-Superconductor (SNS) and weak link (WL) junctions affects the speed, delay, and margin of the AQFP gates. The JJ models are defined in the Keysight ADS simulator using symbolically defined device (SDD) method.
Abstract Superconductor logic families can operate with small power dissipation and are thus suitable as building blocks for various computing systems. In some applications, superconductor logic circuits should be designed using Josephson junctions with low I c values ( I c : critical current). For instance, lowering I c values enables qubit interface circuits to operate with very small power dissipation at ~10 mK and stochastic electronics to easily induce stochastic operations. In this study, we develop the AIST 1 kA cm −2 Nb planarized process (1KP) with a minimum critical current of 10 µA, dedicated to the design of qubit interface circuits and stochastic electronics. We also develop rapid single-flux-quantum (RSFQ) and adiabatic quantum-flux-parametron (AQFP) cell libraries using the 1KP. The power dissipation of RSFQ logic using the 1KP can be reduced to 3.2% of that for conventional RSFQ logic by reducing both I c values and a bias voltage. Furthermore, the amount of supply currents for AQFP circuits using the 1KP can be reduced to ~40% of that for conventional AQFP circuits due to a large mutual inductance between AQFP gates and excitation lines, which results from a reduction in I c and an increase in inductances. We demonstrate RSFQ and AQFP circuits fabricated by the 1KP at 4.2 K. These results indicate that RSFQ and AQFP circuits using the 1KP have the potential to be used for the design of qubit interface circuits and stochastic electronics.
Abstract Adiabatic quantum-flux-parametron (AQFP) is an adiabatic logic based on the quantum-flux-parametron. It has extremely low switching energy, as well as high signal gain and high robustness. In this work, we present the development of an AQFP cell library using the MIT LL 100 μ A μ m −2 superconductor electronics fabrication process, SFQ5ee. Four types of basic sub-cells, i.e. buffer, inverter, constant, and branch, are designed as the building blocks for combinational AQFP logic cells. Taking advantage of the 8 metal layers, we place the dc superconducting quantum interference device (SQUID) part of a buffer above the ground plane and the signal transformer part below the ground plane to mitigate unwanted couplings. In addition, by vertically overlapping the signal transformer and the dc SQUID, the dimension of a buffer is reduced to 15 μ m × 20 μ m, which is only 30% of that of the conventional design. More complex AQFP logic cells, such as the majority gate, AND gate, and OR gate, are designed by arraying the sub-cells together. Correct operations and wide excitation current margins are confirmed for the established AQFP logic cells by both simulation and experiments.