Adiabatic quantum flux parametron (AQFP) gate is a promising approach to scale up the cryogenic microwave electronics for superconducting qubit multiplexed control. However, the performance of these circuits depends on the quality of the Josephson junctions which are ideally superconductor-insulator-superconductor (SIS) type following the ideal sinusoidal relation between current and quantum phase. We demonstrate how the non-sinusoidal current-phase relation in Superconductor-Normal metal-Superconductor (SNS) and weak link (WL) junctions affects the speed, delay, and margin of the AQFP gates. The JJ models are defined in the Keysight ADS simulator using symbolically defined device (SDD) method.
Adiabatic quantum flux parametron (AQFP) gate is a promising approach to scale up the cryogenic microwave electronics for superconducting qubit multiplexed control. However, the performance of these circuits depends on the quality of the Josephson junctions which are ideally superconductor-insulator-superconductor (SIS) type following the ideal sinusoidal relation between current and quantum phase. We demonstrate how the non-sinusoidal current-phase relation in Superconductor-Normal metal-Superconductor (SNS) and weak link (WL) junctions affects the speed, delay, and margin of the AQFP gates. The JJ models are defined in the Keysight ADS simulator using symbolically defined device (SDD) method.
Superconductor/ferromagnet/superconductor Josephson junctions across which the phases of superconducting order parameters are shifted by π in the ground state are called π Josephson junctions (π-JJs). Recently, several groups have established the fabrication technology of π-JJs so that superconductor logic families exploit π-JJs to improve circuit performance. In this paper, we investigate the advantages of π-JJs in adiabatic quantum-flux-parametron (AQFP) logic, which is an adiabatic superconductor logic based on the quantum-flux-parametron. First, we show that AQFP logic with π-JJs (π-AQFP) can operate using only π-JJs and can be powered and clocked in the same way as the conventional AQFP logic. Then, we show that π-AQFP logic can realize inverters without using signal transformers, which generally occupy a large area in AQFP gates and are difficult to miniaturize. We demonstrate π-AQFP inverters using numerical simulation to establish that π-AQFP logic operates adiabatically and robustly. Our results show that π-JJs can be easily incorporated into AQFP logic and enhance the circuit density of AQFP logic.
Adiabatic quantum flux parametron (AQFP) is a very energy-efficient superconductor logic. In AQFP logic, dynamic energy dissipation can be drastically reduced due to adiabatic switching operations using ac excitation currents. In the present study, we evaluated circuit yields using a large-scale AQFP circuit composed of as many as 10,000 AQFP gates with approximately 20,000 Josephson junctions. We measured eleven chips from four wafers and obtained circuit yields of 48% for 1,000-gate circuits and 22% for 10,000-gate circuits, respectively. In all the circuits, which worked correctly, the margins of excitation currents were as wide as approximately ±20%.
Abstract We report on the design and implementation of adiabatic quantum flux parametron (AQFP) buffer gates utilizing cross-type Nb/AlO x /Nb Josephson junctions with I C of 20 μ A, designed to operate at mK temperatures. We, therefore, discuss design considerations, circuit simulation and optimization and their technological implementation. The preliminary results of the test circuit at 4.2 K are demonstrated focusing on the performance. Particularly, we emphasize on the current sensitivity of the circuit based on the output switching probability. The measurement results, show a narrow grayzone width of 0.48 μ A for low-speed operation, demonstrating a higher current sensitivity. Additionally, the designed AQFP circuit exhibits a wide operating margins, further endorsing their potential for high sensitivity based superconducting sensors and scalable interface circuits for quantum electronics.
The adiabatic quantum flux parametron (AQFP) is an energy-efficient, high-speed superconducting logic device. To observe the tiny output currents from the AQFP in experiments, high-speed voltage drivers are indispensable. In the present study, we develop a compact voltage driver for AQFP logic based on a Josephson latching driver (JLD), which has been used as a high-speed driver for rapid single-flux-quantum (RSFQ) logic. In the JLD-based voltage driver, the signal currents of AQFP gates are converted into gap-voltage-level signals via an AQFP/RSFQ interface and a four-junction logic gate. Furthermore, this voltage driver includes only 15 Josephson junctions, which is much fewer than in the case for the previously designed driver based on dc superconducting quantum interference devices (60 junctions). In measurement, we successfully operate the JLD-based voltage driver up to 4 GHz. We also evaluate the bit error rate (BER) of the driver and find that the BER is 7.92×10-10 and 2.67×10-3 at 1GHz and 4GHz, respectively.
Adiabatic quantum-flux-parametron (AQFP) is an ac-biased logic family noted for its extremely low switching energy of around 1.4 zJ per Josephson junction (JJ) at a clock frequency of 5 GHz. Therefore, the AQFP logic family provides a high-speed, ultra-low-energy alternative to CMOS technology. However, quantised flux, such as vortices, trapped in the superconductor film can adversely affect circuit operation. A conventional solution to vortices is the introduction of low potential holes, also known as moats, within the film. Although basic guidelines have been introduced from published circuits, there is currently no standard method for designing and analysing moats for AQFP circuits. The double gate process (DGP) is a double-active-layered niobium fabrication process that allows for more compact circuits. But the effects of quantised flux for AQFP circuits on both active layers are currently unknown. We use 3D parameter extraction software tools to analyse the effect of various moat structures for AQFP logic cells for DGP and improve layout and moat placement designs.
Abstract Adiabatic quantum-flux-parametron (AQFP) logic is an energy-efficient superconductor logic family. The latency of AQFP circuits is relatively long compared to that of other superconductor logic families and thus such circuits require low-latency clocking schemes. In a previous study, we proposed a low-latency clocking scheme called delay-line clocking, in which the latency for each logic operation is determined by the propagation delay of the excitation current, and demonstrated a simple AQFP buffer chain that adopts delay-line clocking. However, it is unclear whether more complex AQFP circuits can adopt delay-line clocking. In the present study, we demonstrate AQFP logic gates (AND and XOR gates) that use delay-line clocking as a step towards implementing large-scale AQFP circuits with delay-line clocking. AND and XOR gates with a latency of approximately 20 ps per gate are shown to operate at up to 5 and 4 GHz, respectively, in experiments. We also demonstrate that delay-line clocking enables phase skipping operation, in which some of the AQFP buffers for phase synchronization are removed to reduce the junction count and energy dissipation. The results indicate that delay-line clocking can enable low-latency, low-energy, large-scale AQFP circuits.