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IEICE Technical Report; IEICE Tech. Rep.

Miniaturization of a 2×2 switch cell toward realization of large-scale SFQ switches

Nakagawa Takahiro, Yoshihito Hashimoto, 義男 亀田, Shinichi Yorozu, Mutsuo Hidaka, Kazunori Miyahara

Published Oct 10, 2007• 0 citations
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We have developed a miniaturized 2times2 switch cell, a key component of single-flux-quantum switches. The cell was optimized using a full-custom design approach instead of our conventional cell-based design approach. The cell contains 74 Josephson junctions, and its power consumption is 16.8 muW. Its area is significantly reduced to 160 mum times 200 mum, which is 69% smaller than our conventional cell-based switch. We fabricated test chips using our 2.5-kA/cm2Nb standard process and confirmed a 40-GHz operation with a bias margin of plusmn8.5% by an on-chip test. We also designed 4times4 and 8times8 cross-bar switches using the 2times2 switch cells. The 40-GHz operation of the 4times4 switch was confirmed with a bias margin of plusmn4% by an on-chip test. The full function of the 8times8 switch was also confirmed with a bias margin of plusmn5% at a low-frequency (10 kHz). The area of these switches was reduced to about half of that of our conventional switches. We discussed large-scale switches using our advanced high- Jc multilayer process. We estimated that area of a 32 times 32 switch designed for the advanced process are reduced by 83% compared to a switch designed for the standard process.
We have been developing a single-flux-quantum (SFQ) cross-bar switch, which is a main component of a network packet switch. We think that a network switch is an application in which the high speed of SFQ technology would be advantageous. Anticipating general and large-scale SFQ logic circuit design, we used the cell-based design method and the CONNECT standard SFQ cell library. The two-input and two-output cross-bar switch, a core switch component, consists of 13 logic cells connected by Josephson-transmission-line (JTL) cells. Because of the large size of JTL cells and the large delay in them, timing adjustment becomes more difficult as the operating speed and circuit size increase. After using a commercially available automatic router to find appropriate routes efficiently, we used a static timing analyzer for fine timing adjustment. Timing violations were fixed by changing JTL path delays using the tools we developed. The target operating frequency of the switch was 40 GHz, which corresponds to a clock period of 25 ps. Careful timing adjustment was necessary to ensure correct operations at such a high speed. The test chip was fabricated by using an NEC standard Nb process. The circuit, including on-chip test circuitry, was composed of about 1500 Josephson junctions. We confirmed its correct operations up to 50 GHz with a bias margin of /spl plusmn/20%.