We have developed a miniaturized 2times2 switch cell, a key component of single-flux-quantum switches. The cell was optimized using a full-custom design approach instead of our conventional cell-based design approach. The cell contains 74 Josephson junctions, and its power consumption is 16.8 muW. Its area is significantly reduced to 160 mum times 200 mum, which is 69% smaller than our conventional cell-based switch. We fabricated test chips using our 2.5-kA/cm2Nb standard process and confirmed a 40-GHz operation with a bias margin of plusmn8.5% by an on-chip test. We also designed 4times4 and 8times8 cross-bar switches using the 2times2 switch cells. The 40-GHz operation of the 4times4 switch was confirmed with a bias margin of plusmn4% by an on-chip test. The full function of the 8times8 switch was also confirmed with a bias margin of plusmn5% at a low-frequency (10 kHz). The area of these switches was reduced to about half of that of our conventional switches. We discussed large-scale switches using our advanced high- Jc multilayer process. We estimated that area of a 32 times 32 switch designed for the advanced process are reduced by 83% compared to a switch designed for the standard process.
We have developed a miniaturized 2times2 switch cell, a key component of single-flux-quantum switches. The cell was optimized using a full-custom design approach instead of our conventional cell-based design approach. The cell contains 74 Josephson junctions, and its power consumption is 16.8 muW. Its area is significantly reduced to 160 mum times 200 mum, which is 69% smaller than our conventional cell-based switch. We fabricated test chips using our 2.5-kA/cm2Nb standard process and confirmed a 40-GHz operation with a bias margin of plusmn8.5% by an on-chip test. We also designed 4times4 and 8times8 cross-bar switches using the 2times2 switch cells. The 40-GHz operation of the 4times4 switch was confirmed with a bias margin of plusmn4% by an on-chip test. The full function of the 8times8 switch was also confirmed with a bias margin of plusmn5% at a low-frequency (10 kHz). The area of these switches was reduced to about half of that of our conventional switches. We discussed large-scale switches using our advanced high- Jc multilayer process. We estimated that area of a 32 times 32 switch designed for the advanced process are reduced by 83% compared to a switch designed for the standard process.
We have been developing a single-flux-quantum (SFQ) cross-bar switch, which is a main component of a network packet switch. We think that a network switch is an application in which the high speed of SFQ technology would be advantageous. Anticipating general and large-scale SFQ logic circuit design, we used the cell-based design method and the CONNECT standard SFQ cell library. The two-input and two-output cross-bar switch, a core switch component, consists of 13 logic cells connected by Josephson-transmission-line (JTL) cells. Because of the large size of JTL cells and the large delay in them, timing adjustment becomes more difficult as the operating speed and circuit size increase. After using a commercially available automatic router to find appropriate routes efficiently, we used a static timing analyzer for fine timing adjustment. Timing violations were fixed by changing JTL path delays using the tools we developed. The target operating frequency of the switch was 40 GHz, which corresponds to a clock period of 25 ps. Careful timing adjustment was necessary to ensure correct operations at such a high speed. The test chip was fabricated by using an NEC standard Nb process. The circuit, including on-chip test circuitry, was composed of about 1500 Josephson junctions. We confirmed its correct operations up to 50 GHz with a bias margin of /spl plusmn/20%.
A single flux quantum (SFQ) logic cell library has been developed for the 10kA/cm2 Nb multi-layer fabrication process to efficiently design large-scale SFQ digital circuits. In the new cell library, the critical current density of Josephson junctions is increased from 2.5kA/cm2 to 10kA/cm2 compared to our conventional cell library, and the McCumber-Stwart parameter of each Josephson junction is increased to 2 in order to increase the circuit operation speed. More than 300 cells have been designed, including fundamental logic cells and wiring cells for passive interconnects. We have measured all cells and confirmed they stably operate with wide operating margins. On-chip high-speed test of the toggle flip-flop (TFF) cell has been performed by measuring the input and output voltages. The TFF cell at the input frequency of up to 400GHz was confirmed to operate correctly. Also, several fundamental digital circuits, a 4-bit concurrent-flow shift register and a bit-serial adder have been designed using the new cell library, and the correct operations of the circuits have been demonstrated at high clock frequencies of more than 100GHz.
Single-flux-quantum (SFQ) technology is a novel technology where binary information is represented by a single flux. It enables us to realize high-speed, low-power SFQ logic circuits, surpassing conventional complementary metal-oxide-silicon (CMOS) technology. We proposed an SFQ packet switch to avoid the bottlenecks in broadband networks of the future. To demonstrate high-speed operation of an SFQ logic circuit and its application to our switch architecture, we designed a cross/bar switch. It consists of 13 logic gates and 581 Josephson junctions were used in the layout. We confirmed correct operations up to 33 GHz in simulation. We placed the switch circuit in an on-chip test system for high-speed (over 10 GHz) test. Including I/O circuits, the system as a whole consists of 1236 Josephson junctions. The chip was fabricated by using NEC's standard Nb process. We carried out an on-chip test and found correct operations up to 35 GHz.
We have developed a cell library for superconducting large scale integrated (LSI) digital circuits based on Single Flux Quantum (SFQ) devices. The circuits were designed for a 6-kA/cm2Nb/AlOx/Nb junction process with 10 mask levels including one ground plane and two Nb wiring layers. The initial design and optimization of the circuit parameters were achieved by means of the optimization functions in a circuit simulator, PSCAN2, to ensure that important circuit parameters, Josephson critical current (IC), bias current (Ibias), and inductance satisfied minimal margin requirements. Critical margins of ICand Ibiaswere then further improved manually. To compensate the scattering in the circuit parameters from fabrication by design as much as possible, the critical junction parameters were optimized to further centralize the IC. The library cells were laid out following our design rules determined by systematic experiments on process control monitors (PCM). Basic cells including Josephson transmission lines, splitters, confluence buffers, D flip-flops, T flip-flops, and XOR and NDRO gates were designed, fabricated, and successfully tested at low frequencies. Wide overlaps of the operating regions for the common bias voltages were confirmed.
Single flux quantum (SFQ) technology has garnered significant attention due to its low switching power and high operational speed. Researchers have been actively pursuing more advanced devices and technologies to further reduce the reliance on inductors, bias, and dynamic power. Recently, innovative magnetic Josephson junction devices have emerged, enhancing the field of superconductor electronics logic. This article introduces a novel cell library design that relies entirely on Josephson junctions, showing promising potential for eliminating the need for inductors in conventional SFQ cells. This results in a 55% reduction in cell size and an 80% decrease in both static and dynamic power consumption. The proposed library implements a half flux quantum logic, where each pulse duration is half that of a SFQ pulse. This article presents the schematics of the basic cells, emphasizing critical circuit parameters and their margins. In addition, it examines layout blueprints, showcasing the advantageous area-saving characteristics of the proposed design.
A single-flux-quantum (SFQ) device provides fast operation with low power consumption. As SFQ devices can be applied in network switches requiring high throughput, we have been developing an SFQ network switch system. Not only the switch fabric but also the switch scheduler is a key component for a high-throughput network switch. The switch scheduler orders multiple inputs to a single output at the same time to prevent collisions from occurring in the switch fabric. The scheduling time becomes longer as the number of switch ports increases, because the scheduler must scan requests from all input ports. We designed two types of 4-port arbiters (i.e. switch scheduler sub-circuits) with structures based on serial or parallel processing. We chose to implement and demonstrate the serial arbiter because it has a smaller number of gates. It consisted of about 1800 Josephson junctions, including on-chip test circuitry. We tested a fabricated circuit at high speed and confirmed its correct operation at 40 GHz.