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IEICE Transactions on Electronics

A Hybrid Switch System Architecture for Large-Scale Digital Communication Network Using SFQ Technology

Shinichi Yorozu, 義男 亀田, Shuichi Tahara

Published Jan 1, 2001• 5 citations
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I describe the fundamental technologies concerning the single flux quantum (SFQ) logic circuits. Recent remarkable progress in the computer-aided-design (CAD) tool, which is based on the cell-based design technique, enables us to make SFQ integrated circuits. Although the circuit demonstrated so far has 2, 300 Josephson junctions at most, this number will increase because the CAD tool is advancing. The on-chip test system has also been developed to test the high-speed nature of the SFQ circuit. For example, the shift-register employed as a circuit under test operates correctly at 55GHz. I also describe the potential applications of the SFQ circuits. An analog-to-digital converter utilizing the high-speed nature and high sensitivity in the SFQ circuits will be applicable to the front end of the future base stations, which require broad band width, high sensitivity, and flexibility. Packet switches used in the future high-end router need high throughput and functionality. Only SFQ-based packet switches can meet these requirements. Another potential application is a high-end server. We have studied micro-architectures of a processor executing the Java Byte Codes directly and a multiprocessor system constructed by connecting the processors and memories via the ultra-broad-band SFQ network switches. Throughout the study, we employ the concept of the complexity-reduction (CORE), in which the high-speed nature of the SFQ circuits is used for the reduction of the circuit scale or simplification of the micro-architecture; the multiprocessor system has high performances. These clear applications promote rapid technological progress in the SFQ technology, though we must make every endeavor to find new application fields.

TEION KOGAKU (Journal of Cryogenics and Superconductivity Society of Japan)•Jan 1, 2001•0 citations
Large-scale telecommunication systems in the larger nationwide network of the next decade will require routers having a packet switching throughput capacity of over several-tens Tbps. In such future high-end routers, the packet switch, which is the biggest bottleneck of the router, will need higher processing speeds than semiconductor devices. In this paper, we describe an SFQ packet switch architecture that is used in the internal speed-up Banyan network. According to the architecture we have designed and demonstrated a deep-pipelined 2/spl times/2 packet switch logic circuit, which is the key element in a packet switch, by applying two technological advances regarding design methodology and packaging. This circuit is among the largest SFQ random logic circuits yet reported.
Superconducting devices have intrinsically superior characteristics to those of semiconductor devices. Presently, we can fabricate more than twenty thousand junctions on one chip using niobium technology. We have demonstrated the operation of a network system with a superconducting interconnection chip using voltage-state logic. Single flux quantum devices are promising for future superconducting applications because the clock frequency of SFQ logic is higher than that of voltage-state. We have proposed a high-end switch based on hybrid architecture using optical devices, semiconductors and SFQ devices. To demonstrate the high-speed operation of SFQ circuits, we developed an arbiter circuit that uses SFQ components and the arbiter circuit operates at 60 GHz. We also have developed a high Tc superconducting (HTS) SFQ sampler system for observing ultra-fast signal waveforms. In addition, we will discuss the prospects of future superconducting devices based on the fabrication technologies we developed.
I describe the fundamental technologies concerning the single flux quantum (SFQ) logic circuits. Recent remarkable progress in the computer-aided-design (CAD) tool, which is based on the cell-based design technique, enables us to make SFQ integrated circuits. Although the circuit demonstrated so far has 2, 300 Josephson junctions at most, this number will increase because the CAD tool is advancing. The on-chip test system has also been developed to test the high-speed nature of the SFQ circuit. For example, the shift-register employed as a circuit under test operates correctly at 55GHz. I also describe the potential applications of the SFQ circuits. An analog-to-digital converter utilizing the high-speed nature and high sensitivity in the SFQ circuits will be applicable to the front end of the future base stations, which require broad band width, high sensitivity, and flexibility. Packet switches used in the future high-end router need high throughput and functionality. Only SFQ-based packet switches can meet these requirements. Another potential application is a high-end server. We have studied micro-architectures of a processor executing the Java Byte Codes directly and a multiprocessor system constructed by connecting the processors and memories via the ultra-broad-band SFQ network switches. Throughout the study, we employ the concept of the complexity-reduction (CORE), in which the high-speed nature of the SFQ circuits is used for the reduction of the circuit scale or simplification of the micro-architecture; the multiprocessor system has high performances. These clear applications promote rapid technological progress in the SFQ technology, though we must make every endeavor to find new application fields.