Proposing an architecture that efficiently compensates for the inefficiencies of physical hardware with extra resources is one of the key issues in quantum computer design. Although the demonstration of quantum systems has been limited to some dozen qubits, scaling the current small-sized lab quantum systems to large-scale quantum systems that are capable of solving meaningful practical problems can be the main goal of much research. Focusing on this issue, in this article a scalable architecture for quantum information processors, called SAQIP, is proposed. Moreover, a flow is presented to map and schedule a quantum circuit on this architecture. Experimental results show that the proposed architecture and design flow decrease the average latency and the average area of quantum circuits by about 81% and 11%, respectively, for the attempted benchmarks.
Proposing an architecture that efficiently compensates for the inefficiencies of physical hardware with extra resources is one of the key issues in quantum computer design. Although the demonstration of quantum systems has been limited to some dozen qubits, scaling the current small-sized lab quantum systems to large-scale quantum systems that are capable of solving meaningful practical problems can be the main goal of much research. Focusing on this issue, in this article a scalable architecture for quantum information processors, called SAQIP, is proposed. Moreover, a flow is presented to map and schedule a quantum circuit on this architecture. Experimental results show that the proposed architecture and design flow decrease the average latency and the average area of quantum circuits by about 81% and 11%, respectively, for the attempted benchmarks.
Proposing an architecture that effectively compensates for physical hardware inefficiencies through redundant resources is a key challenge in quantum computer design. Although the representation of quantum systems is currently limited to tens of qubits, scaling existing small scale laboratory systems into large scale quantum computers capable of solving meaningful practical problems remains a primary research objective. Focusing on this issue, this paper proposes a scalable architecture for quantum information processors. Physical design, one of the two main processes in quantum computer design, transforms a circuit netlist into a technology specific layout. Quantum mapping comprising partitioning, placement, scheduling, and routing is an essential part of this process, and these stages are inherently interdependent. In this research, considering the dependencies between these stages, we present an Integer Linear Programming (ILP) model for qubit partitioning and placement, determining the optimal module and physical location for each qubit. Furthermore, we propose a heuristic approach for the placement and scheduling of quantum operators on a scalable, modular, universal ion trap quantum computer (MUSIQC), aiming to minimize circuit execution delay. Qubit routing is performed using a greedy strategy. For evaluation, the proposed method was applied to both Ripple-Carry Adder and Carry-Lookahead Adder circuits. Experimental results demonstrate that the proposed approach reduces the average circuit delay by approximately 58.98% for Ripple-Carry Adder circuits and 33% for Carry-Lookahead Adder circuits compared to the best existing method. These results underscore the effectiveness of our integrated framework, where ILP-based partitioning optimizes for dominant operational costs, while our subsequent resource-aware scheduler actively manages parallelism and contention to achieve the minimal overall circuit execution delay.
Quantum computing benefits from collective features of quantum states, such as superposition and entanglement, to efficiently address problems that are very hard to be solved on classical systems. The Scalable Architecture for Quantum Information Processor (SAQIP) architecture is a promising technology that is based on ion-traps and realizes a hybrid composed of a large number of full-custom building blocks (supposed to realize so-called Elementary Logic Units; ELUs) connected by a reconfigurable optical switch network. As with every architecture, corresponding design methods are required in order to properly map a given quantum functionality onto the respective device. However, since the corresponding complexity frequently made exact solutions for this task infeasible for past architectures, most of the existing mapping methods rely on heuristics and, hence, do not provide exact/optimal results. Considering the SAQIP architecture, however, this problem can be prevented. In fact, due to the building blocks of this architecture, any circuit to be mapped has to be partitioned into ELUs anyway. Since those are usually of moderate size, exact/optimal solutions for them are possible. In this work, we sketch an exact mapping method that can generate such optimal results. To this end, we propose a corresponding formulation in mixed-integer linear programming (MILP) that allows to cope with the (smaller, but still not non-trivial) complexity.
Quantum computing has the potential to solve complex problems that are outside the scope of classical systems, making it a standard shifter. Current devices, which are considered as Noisy Intermediate-Scale Quantum (NISQ) systems, are insufficient in their practical utility due to hardware limitations, error rates, and qubit counts. The dynamic growths wanted to exceed the NISQ era and grow scalable quantum algorithms and architectures that can achieve useful quantum benefit in real-world applications are reviewed in this research. This research gives a comprehensive examination of the complications in scaling quantum systems, adjacent resource efficacy, qubit connectivity, and error correction. In addition to connecting architectural innovations like modular quantum computing, error-resilient circuit design, and distributed quantum systems, the paper provides new hybrid quantum-classical algorithms planned to exploit performance in noisy environments. Results from benchmarking in arenas like machine learning, optimization, and quantum chemistry show how these methods can provide short-term quantum benefit. Lastly, this paper proposes a research roadmap for quantum computing that highlights the requirement of co-designing algorithms, software, and hardware. The goal of this effort is to straighten the progress of quantum systems that can resolve problems in the real world at scale by addressing the inadequacies of NISQ devices and emphasizing scalable solutions.
Current approaches for emulation of quantum algorithms on classical parallel hardware like FPGA suffer with three main issues: exponential usage of logic elements, synthesis takes exponential time and difficulty of implementation. In this paper we propose a processor architecture capable of efficiently emulate quantum circuits, reducing the mishaps of previous similar proposals. We compare our results to previous works with respect to a common benchmark and validate the architecture using FPGA. Our approach has better scalability in logic cell usage, a better management of the need of re-synthesis and easier implementation.
The challenge of building scalable quantum computer lies in striking appropriate balance between designing a reliable system architecture from large number of faulty computational resources and improving the physical quality of system components. The detailed investigation of performance variation with physics of the components and the system architecture requires adequate performance simulation tool. In this thesis we demonstrate a software tool capable of (1) mapping and scheduling the quantum circuit on a realistic quantum hardware architecture with physical resource constraints, (2) evaluating the performance metrics such as the execution time and the success probability of the algorithm execution, and (3) analyzing the constituents of these metrics and visualizing resource utilization to identify system components which crucially define the overall performance. Using this versatile tool, we explore vast design space for modular quantum computer architecture based on trapped ions. We find that while success probability is uniformly determined by the fidelity of physical quantum operation, the execution time is a function of system resources invested at various layers of design hierarchy. At physical level, the number of lasers performing quantum gates, impact the latency of the fault-tolerant circuit blocks execution. When these blocks are used to construct meaningful arithmetic circuit such as quantum adders, the number of ancilla qubits for complicated non-clifford gates and entanglement resources to establish long-distance communication channels, become major performance limiting factors. Next, in order to factorize large integers, these adders are assembled into modular exponentiation circuit comprising bulk of Shor's algorithm. At this stage, the overall scaling of resource-constraint performance with the size of problem, describes the effectiveness of chosen design. By matching the resource investment with the pace of advancement in hardware technology, we find optimal designs for different types of quantum adders. Conclusively, we show that 2,048-bit Shor's algorithm can be reliably executed within the resource budget of 1.5 million qubits.
This thesis addresses the design of a quantum computer (QC) architecture. Quantum error correction is a dominant factor as it is required to protect quantum bits (qubits) from decoherence. However, error correction's costs are substantial and call for a scale-up of 100X more qubits and instruction-level parallelism (ILP) on the order of 10,000 simultaneous operations per cycle. These are daunting challenges for a QC architect, who must balance demands in performance, control efficiency, and scalability of design.
Error modeling is important for designing a QC so that error correction implementations and microarchitecture designs may be evaluated for effectiveness. This thesis presents a new deterministic approach to error modeling that is on the order of 1000X faster than previous Monte Carlo error models. While the deterministic error model is memory limited, it is capable of evaluating useful problems containing on the order of a dozen logical qubits encoded in the [[7,1,3]] quantum error correcting code (QECC).
This dissertation presents a new QC processor architecture that leverages highly mobile qubits found in some QC technologies such as electron-spins on liquid helium (eSHe). The processor architecture presented here is designed to efficiently handle at least an order of magnitude more ILP than previously proposed designs, and it accommodates increasing ILP with size and latency costs scaling only linearly. Compilers are also crucial to a computer's performance and efficiency, and this dissertation describes new compiler optimizations including one that reduces hardware requirements by 25% with no performance loss.
Multiple QC processors may be organized into a tiled configuration to provide sufficient ILP across the entire QC. This dissertation proposes a new distributed block tiling strategy that distributes encoded block qubits across arrays of data tiles and offloads non-critical path error correction routines to separate ancilla tiles. This strategy reduces tile capacity requirements by over 100X with the [[21,3,5]] QECC and achieves a simulated speedup of 2.8X for the eSHe QC when compared to the traditional tiling approach.
In summary, this dissertation presents a novel QC architecture and design tools that improve performance and scalability while making efficient use of both control and qubit resources.