Quantum computing benefits from collective features of quantum states, such as superposition and entanglement, to efficiently address problems that are very hard to be solved on classical systems. The Scalable Architecture for Quantum Information Processor (SAQIP) architecture is a promising technology that is based on ion-traps and realizes a hybrid composed of a large number of full-custom building blocks (supposed to realize so-called Elementary Logic Units; ELUs) connected by a reconfigurable optical switch network. As with every architecture, corresponding design methods are required in order to properly map a given quantum functionality onto the respective device. However, since the corresponding complexity frequently made exact solutions for this task infeasible for past architectures, most of the existing mapping methods rely on heuristics and, hence, do not provide exact/optimal results. Considering the SAQIP architecture, however, this problem can be prevented. In fact, due to the building blocks of this architecture, any circuit to be mapped has to be partitioned into ELUs anyway. Since those are usually of moderate size, exact/optimal solutions for them are possible. In this work, we sketch an exact mapping method that can generate such optimal results. To this end, we propose a corresponding formulation in mixed-integer linear programming (MILP) that allows to cope with the (smaller, but still not non-trivial) complexity.
Quantum computing benefits from collective features of quantum states, such as superposition and entanglement, to efficiently address problems that are very hard to be solved on classical systems. The Scalable Architecture for Quantum Information Processor (SAQIP) architecture is a promising technology that is based on ion-traps and realizes a hybrid composed of a large number of full-custom building blocks (supposed to realize so-called Elementary Logic Units; ELUs) connected by a reconfigurable optical switch network. As with every architecture, corresponding design methods are required in order to properly map a given quantum functionality onto the respective device. However, since the corresponding complexity frequently made exact solutions for this task infeasible for past architectures, most of the existing mapping methods rely on heuristics and, hence, do not provide exact/optimal results. Considering the SAQIP architecture, however, this problem can be prevented. In fact, due to the building blocks of this architecture, any circuit to be mapped has to be partitioned into ELUs anyway. Since those are usually of moderate size, exact/optimal solutions for them are possible. In this work, we sketch an exact mapping method that can generate such optimal results. To this end, we propose a corresponding formulation in mixed-integer linear programming (MILP) that allows to cope with the (smaller, but still not non-trivial) complexity.
Quantum computers exploit quantum effects in a controlled manner in order to efficiently solve problems that are very hard to address on classical computers. The ion-trap-based technology is a particularly advanced concept of realizing quantum computers with advantages with respect to physical realization and fault-tolerance. Accordingly, several physical design methods aiming at realizing quantum circuits to corresponding architectures have been proposed. However, all these methods are heuristic and cannot guarantee minimality. In this work, we propose a solution which can generate exact physical designs, i.e., solutions which require a minimal number of time steps. To this end, satisfiability solvers are utilized. Experimental evaluations confirm that, despite the underlying computational complexity of the problem, this allows to generate minimal physical designs for several quantum circuits for the first time.
Proposing an architecture that efficiently compensates for the inefficiencies of physical hardware with extra resources is one of the key issues in quantum computer design. Although the demonstration of quantum systems has been limited to some dozen qubits, scaling the current small-sized lab quantum systems to large-scale quantum systems that are capable of solving meaningful practical problems can be the main goal of much research. Focusing on this issue, in this article a scalable architecture for quantum information processors, called SAQIP, is proposed. Moreover, a flow is presented to map and schedule a quantum circuit on this architecture. Experimental results show that the proposed architecture and design flow decrease the average latency and the average area of quantum circuits by about 81% and 11%, respectively, for the attempted benchmarks.
Proposing an architecture that effectively compensates for physical hardware inefficiencies through redundant resources is a key challenge in quantum computer design. Although the representation of quantum systems is currently limited to tens of qubits, scaling existing small scale laboratory systems into large scale quantum computers capable of solving meaningful practical problems remains a primary research objective. Focusing on this issue, this paper proposes a scalable architecture for quantum information processors. Physical design, one of the two main processes in quantum computer design, transforms a circuit netlist into a technology specific layout. Quantum mapping comprising partitioning, placement, scheduling, and routing is an essential part of this process, and these stages are inherently interdependent. In this research, considering the dependencies between these stages, we present an Integer Linear Programming (ILP) model for qubit partitioning and placement, determining the optimal module and physical location for each qubit. Furthermore, we propose a heuristic approach for the placement and scheduling of quantum operators on a scalable, modular, universal ion trap quantum computer (MUSIQC), aiming to minimize circuit execution delay. Qubit routing is performed using a greedy strategy. For evaluation, the proposed method was applied to both Ripple-Carry Adder and Carry-Lookahead Adder circuits. Experimental results demonstrate that the proposed approach reduces the average circuit delay by approximately 58.98% for Ripple-Carry Adder circuits and 33% for Carry-Lookahead Adder circuits compared to the best existing method. These results underscore the effectiveness of our integrated framework, where ILP-based partitioning optimizes for dominant operational costs, while our subsequent resource-aware scheduler actively manages parallelism and contention to achieve the minimal overall circuit execution delay.
This paper addresses the challenge of scaling quantum computing by employing distributed quantum algorithms across multiple processors. As quantum circuits grow in complexity, efficiently managing the entanglement resources required for communication between quantum processing units (QPUs) becomes increasingly critical. We propose novel methods to optimize entanglement consumption while accounting for network constraints. Our approach leverages graph partitioning techniques to optimize both qubit teleportation and gate teleportation, minimizing the number of Einstein-Podolsky-Rosen (EPR) pairs required to execute general quantum circuits. Additionally, we formulate an integer linear program (ILP) to further reduce entanglement requirements by mapping the logical resources of partitioned circuits to the physical constraints of the underlying quantum network. Finally, we analyze the entanglement cost for implementing the Quantum Fourier Transform (QFT) across multiple QPUs, employing an approach that exploits the circuit's structure to minimize total entanglement consumption. These contributions provide a pathway to scalable and resource-efficient distributed quantum computing.
Compiling a high-level quantum circuit down to a low-level description that can be executed on state-of-the-art quantum computers is a crucial part of the software stack for quantum computing. One step in compiling a quantum circuit to some device is quantum circuit mapping, where the circuit is transformed such that it complies with the architecture’s limited qubit connectivity. Because the search space in quantum circuit mapping grows exponentially in the number of qubits, it is desirable to consider as few of the device’s physical qubits as possible in the process. Previous work conjectured that it suffices to consider only subarchitectures of a quantum computer composed of as many qubits as used in the circuit. In this work, we refute this conjecture and establish criteria for judging whether considering larger parts of the architecture might yield better solutions to the mapping problem. We show that determining subarchitectures that are of minimal size, i.e., from which no physical qubit can be removed without losing the optimal mapping solution for some quantum circuit, is a very hard problem. Based on a relaxation of the criteria for optimality, we introduce a relaxed consideration that still maintains optimality for practically relevant quantum circuits. Eventually, this results in two methods for computing near-optimal sets of subarchitectures—providing the basis for efficient quantum circuit mapping solutions. We demonstrate the benefits of this novel method for state-of-the-art quantum computers by IBM, Google, and Rigetti.
Noisy intermediate scale quantum (NISQ) computers are becoming a reality thanks to the recent advances made by researchers who physically build such systems. In order to execute corresponding quantum algorithms (usually provided in terms of quantum circuits), certain physical constraints in the architectures need to be satisfied. More precisely, physical constraints restrict the possible interactions between qubits which frequently result in cases where qubits which are supposed to interact in a quantum circuit are not allowed to interact on the physical device. Thus far, this is addressed by dedicated methods that map the logical quantum circuit to a physical realization and satisfy the constraints by inserting further operations. This leads to additional costs which harm the fidelity of the circuit and, hence, urgently need to be avoided. Unfortunately, current state-of-the-art approaches for this mapping process take the existing architectures as invariant and only try to reduce the number of additionally needed operations. In contrast, (slight) changes in the, respectively, given architectures (which still keep the underlying physical constraints satisfied) might be possible and may allow for even better (i.e., less costly) mappings. But this potential has not been investigated yet. In this work, we explore this potential. More precisely, we introduce several schemes for generating alternative coupling graphs (and, by this, quantum computing architectures) that still might be able to satisfy physical constraints but, at the same time, allow for a more efficient realization of the desired quantum functionality. Evaluations confirm the potential of those alternative coupling graphs and demonstrate that they can reduce the mapping overhead by up to 60% in the best case and up to almost 40% on average.