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EPJ Quantum Technology

A scalable architecture for quantum information processors: qubit partitioning, placement, and scheduling for minimized circuit latency

Zahra Alimohammadi, Naser Mohammadzadeh, Saeid Seyedi, Hatam Abdoli

Published May 13, 2026• 0 citations
Publisher

Abstract

Proposing an architecture that effectively compensates for physical hardware inefficiencies through redundant resources is a key challenge in quantum computer design. Although the representation of quantum systems is currently limited to tens of qubits, scaling existing small scale laboratory systems into large scale quantum computers capable of solving meaningful practical problems remains a primary research objective. Focusing on this issue, this paper proposes a scalable architecture for quantum information processors. Physical design, one of the two main processes in quantum computer design, transforms a circuit netlist into a technology specific layout. Quantum mapping comprising partitioning, placement, scheduling, and routing is an essential part of this process, and these stages are inherently interdependent. In this research, considering the dependencies between these stages, we present an Integer Linear Programming (ILP) model for qubit partitioning and placement, determining the optimal module and physical location for each qubit. Furthermore, we propose a heuristic approach for the placement and scheduling of quantum operators on a scalable, modular, universal ion trap quantum computer (MUSIQC), aiming to minimize circuit execution delay. Qubit routing is performed using a greedy strategy. For evaluation, the proposed method was applied to both Ripple-Carry Adder and Carry-Lookahead Adder circuits. Experimental results demonstrate that the proposed approach reduces the average circuit delay by approximately 58.98% for Ripple-Carry Adder circuits and 33% for Carry-Lookahead Adder circuits compared to the best existing method. These results underscore the effectiveness of our integrated framework, where ILP-based partitioning optimizes for dominant operational costs, while our subsequent resource-aware scheduler actively manages parallelism and contention to achieve the minimal overall circuit execution delay.

DOI
10.1140/epjqt/s40507-026-00519-6

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Quantum computers will potentially be able to solve certain classes of problems more efficiently than possible on a classical computer. Due to the fragility of quantum data, a large scale quantum computer will require a robust system to enable reliable communication within the datapath. We present a scalable architecture for a quantum computer which specifically addresses communication concerns. Our design minimizes communication error by using a specialized interconnection network to perform long-distance movement. We developed a set of tools to construct and study quantum datapath designs based on ion trap quantum technology. Our tools automatically synthesize and insert the interconnection network used for long-distance communication into the target datapath. We present a set of greedy heuristics to optimize the routing and scheduling of communication within this network and show that our approach performs as well as an optimal case determined using integer linear programming. We study a number of different quantum circuits including randomly generated circuits, quantum adder circuits, and ultimately Shor's factorization algorithm and show that designs using our optimizations significantly improve upon prior work in terms of a probabilistic area delay metric.
Abstract This paper presents a physical mapping tool for quantum circuits, which generates the optimal Universal Logic Block (ULB) that can, on average, perform any logical fault-tolerant (FT) quantum operations with the min-imum latency. The operation scheduling, placement, and qubit routing problems tackled by the quantum physical mapper are highly dependent on one another. More precisely, the scheduling solution affects the quality of the achievable placement solution due to resource pressures that may be created as a result of operation scheduling whereas the operation placement and qubit routing solutions influence the scheduling solution due to resulting distances between predecessor and current operations, which in turn determines routing latencies. The proposed flow for the quantum physical mapper captures these dependencies by applying (i) a loose scheduling step, which transforms an initial quantum data flow graph into one that explicitly captures the no-cloning theorem of the quan-tum computing and then performs instruction scheduling based on a modified force-directed scheduling approach to minimize the resource contention and quantum circuit latency, (ii) a placement step, which uses timing-driven instruction placement to minimize the approximate routing latencies while making iterative calls to the aforesaid force-directed scheduler to correct scheduling levels of quantum operations as needed, and (iii) a routing step that finds dynamic values of routing latencies for the qubits. In addition to the quantum physical mapper, an approach is presented to determine the single best ULB size for a target quantum circuit by examining the latency of different
Abstract The inherent power of quantum computing in parallelizing computations makes it possible to solve some specific problems in a much shorter time than classical computing. Considering the physical issues governing this type of computing, one of the approaches to increase the scalability of such systems is using distributed quantum architectures. A quantum algorithm requires a quantum circuit for a successful implementation. The quantum circuit design flow comprises two main parts: logical synthesis and physical design. Physical synthesis is one of the main steps of the physical design. It improves circuit metrics such as latency and area by changing the netlist or the layout using the information obtained from the initial layout and scheduling. In this paper, we have presented a new physical synthesis method to reduce the quantum circuit delay in distributed architectures. It moves some gates from one partition to another to reduce the number of teleportation operations on the critical path using the scheduled layout information. The experimental results show that this method improves the delay of benchmark circuits on average by 33.40%.