Abstract The inherent power of quantum computing in parallelizing computations makes it possible to solve some specific problems in a much shorter time than classical computing. Considering the physical issues governing this type of computing, one of the approaches to increase the scalability of such systems is using distributed quantum architectures. A quantum algorithm requires a quantum circuit for a successful implementation. The quantum circuit design flow comprises two main parts: logical synthesis and physical design. Physical synthesis is one of the main steps of the physical design. It improves circuit metrics such as latency and area by changing the netlist or the layout using the information obtained from the initial layout and scheduling. In this paper, we have presented a new physical synthesis method to reduce the quantum circuit delay in distributed architectures. It moves some gates from one partition to another to reduce the number of teleportation operations on the critical path using the scheduled layout information. The experimental results show that this method improves the delay of benchmark circuits on average by 33.40%.
Abstract The inherent power of quantum computing in parallelizing computations makes it possible to solve some specific problems in a much shorter time than classical computing. Considering the physical issues governing this type of computing, one of the approaches to increase the scalability of such systems is using distributed quantum architectures. A quantum algorithm requires a quantum circuit for a successful implementation. The quantum circuit design flow comprises two main parts: logical synthesis and physical design. Physical synthesis is one of the main steps of the physical design. It improves circuit metrics such as latency and area by changing the netlist or the layout using the information obtained from the initial layout and scheduling. In this paper, we have presented a new physical synthesis method to reduce the quantum circuit delay in distributed architectures. It moves some gates from one partition to another to reduce the number of teleportation operations on the critical path using the scheduled layout information. The experimental results show that this method improves the delay of benchmark circuits on average by 33.40%.
During the physical design process, the second process of the quantum circuit design flow, using some optimization techniques after layout generation might be useful to improve the metrics or meet the design constraints. Focusing on this issue, this paper proposes an optimization technique using gate location changing to improve the latency of quantum circuits. The proposed technique uses layout and scheduling information to find critical paths and improve their latency by changing locations of the gates on the critical paths. Experimental results show that the proposed technique decreases the latency of quantum circuits up to 26% for the attempted benchmarks.
Quantum circuit design flow consists of two main tasks: synthesis and physical design. Synthesis converts the design description into a technology-dependent netlist and then, physical design takes the fixed netlist, produces the layout, and schedules the netlist on the layout. Quantum physical design problem is intractable. This process can be divided into two main processes: scheduling and layout generation. Some heuristic techniques have been proposed for the layout generation. These techniques do not produce good layouts for large netlists in terms of latency. Focusing on this issue, in this paper, a hierarchical layout generation algorithm is proposed that generates better layouts in terms of latency. Ion trap is used as the underlying technology in this paper. Experimental results show that the proposed algorithm decreases the average latency of quantum circuits by about 22% for the attempted benchmarks.
Quantum computing is expected to become a foundational technology for solving problems that exceed the capabilities of classical systems. As quantum algorithms and hardware technologies continue to advance, the need for scalable architectures becomes increasingly clear. Distributed quantum computing offers a promising path forward by interconnecting multiple smaller processors into a larger, more powerful system. However, distributed quantum computing introduces significant circuit depth overhead, as logical operations are typically decomposed into sequential physical procedures that require entanglement generation. These sequential operations limit the reliability of quantum algorithms in the NISQ era due to noise. In this work, we present a compiler that integrates logical-to-physical decomposition with depth-aware rescheduling to reduce the execution cost of distributed quantum circuits. The compiler identifies sequences of logical CNOT gates that share a control or target qubit, reschedules them into parallel instruction groups, and applies decompositions that allow multiple gates to be executed simultaneously using distributed shared entanglement resources. An algorithm is proposed that ensures parallelism is created when possible while keeping logical equivalence and that circuit depth is never increased. Benchmark results demonstrate that the compiler consistently reduces circuit depth for circuits containing inherently sequential CNOT structures, while leaving already-parallel circuits unchanged. These results highlight the value of combining scheduling and hardware-aware decomposition, and establish the compiler as a practical tool for improving the fidelity of distributed quantum computations.
Quantum circuit design flow consists of two main tasks: synthesis and physical design. In the current flows, two procedures are performed subsequently; synthesis converts the design description into a technology-dependent netlist and then physical design takes the fixed netlist, produces layout, and schedules the netlist on the layout. This style of design suffers from limiting the optimization process in the physical design stage, whereas using a flexible netlist and changing it locally during physical design using layout information often can provide more chance to optimize quantum circuit metrics. Focusing on this issue, in this paper, we propose an optimization flow using gate exchanging heuristic to improve the latency of quantum circuits. We have chosen ion trap technology as the underlying technology to study our flow. Our experimental results show that the proposed flow decreases the latency of quantum circuit by about 23% for the attempted benchmarks.
Proposing an architecture that effectively compensates for physical hardware inefficiencies through redundant resources is a key challenge in quantum computer design. Although the representation of quantum systems is currently limited to tens of qubits, scaling existing small scale laboratory systems into large scale quantum computers capable of solving meaningful practical problems remains a primary research objective. Focusing on this issue, this paper proposes a scalable architecture for quantum information processors. Physical design, one of the two main processes in quantum computer design, transforms a circuit netlist into a technology specific layout. Quantum mapping comprising partitioning, placement, scheduling, and routing is an essential part of this process, and these stages are inherently interdependent. In this research, considering the dependencies between these stages, we present an Integer Linear Programming (ILP) model for qubit partitioning and placement, determining the optimal module and physical location for each qubit. Furthermore, we propose a heuristic approach for the placement and scheduling of quantum operators on a scalable, modular, universal ion trap quantum computer (MUSIQC), aiming to minimize circuit execution delay. Qubit routing is performed using a greedy strategy. For evaluation, the proposed method was applied to both Ripple-Carry Adder and Carry-Lookahead Adder circuits. Experimental results demonstrate that the proposed approach reduces the average circuit delay by approximately 58.98% for Ripple-Carry Adder circuits and 33% for Carry-Lookahead Adder circuits compared to the best existing method. These results underscore the effectiveness of our integrated framework, where ILP-based partitioning optimizes for dominant operational costs, while our subsequent resource-aware scheduler actively manages parallelism and contention to achieve the minimal overall circuit execution delay.