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CSI International Symposium on Computer Architecture and Digital Systems (CADS)

A hierarchical layout generation method for quantum circuits

Mina Chookhachizadeh Moghadam, Naser Mohammadzadeh, Mehdi Sedighi, Morteza Saheb Zamani

Published Oct 1, 2013• 7 citations
Publisher

Abstract

Quantum circuit design flow consists of two main tasks: synthesis and physical design. Synthesis converts the design description into a technology-dependent netlist and then, physical design takes the fixed netlist, produces the layout, and schedules the netlist on the layout. Quantum physical design problem is intractable. This process can be divided into two main processes: scheduling and layout generation. Some heuristic techniques have been proposed for the layout generation. These techniques do not produce good layouts for large netlists in terms of latency. Focusing on this issue, in this paper, a hierarchical layout generation algorithm is proposed that generates better layouts in terms of latency. Ion trap is used as the underlying technology in this paper. Experimental results show that the proposed algorithm decreases the average latency of quantum circuits by about 22% for the attempted benchmarks.

DOI
10.1109/cads.2013.6714237

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Quantum circuit design flow consists of two main tasks: synthesis and physical design. Synthesis converts the design description into a technology-dependent netlist and then, physical design takes the fixed netlist, produces the layout, and schedules the netlist on the layout. Quantum physical design problem is intractable. This process can be divided into two main processes: scheduling and layout generation. Some heuristic techniques have been proposed for the layout generation. These techniques do not produce good layouts for large netlists in terms of latency. Focusing on this issue, in this paper, a hierarchical layout generation algorithm is proposed that generates better layouts in terms of latency. Ion trap is used as the underlying technology in this paper. Experimental results show that the proposed algorithm decreases the average latency of quantum circuits by about 22% for the attempted benchmarks.
Quantum circuit design flow consists of two main tasks: synthesis and physical design. In the current flows, two procedures are performed subsequently; synthesis converts the design description into a technology-dependent netlist and then physical design takes the fixed netlist, produces layout, and schedules the netlist on the layout. This style of design suffers from limiting the optimization process in the physical design stage, whereas using a flexible netlist and changing it locally during physical design using layout information often can provide more chance to optimize quantum circuit metrics. Focusing on this issue, in this paper, we propose an optimization flow using gate exchanging heuristic to improve the latency of quantum circuits. We have chosen ion trap technology as the underlying technology to study our flow. Our experimental results show that the proposed flow decreases the latency of quantum circuit by about 23% for the attempted benchmarks.
Implementing large-scale quantum circuits is one of the challenges of quantum computing. One of the central challenges of accurately modeling the architecture of these circuits is to schedule a quantum application and generate the layout while taking into account the cost of communications and classical resources as well as the maximum exploitable parallelism. In this paper, we present and evaluate a design flow for arbitrary quantum circuits in ion trap technology. Our design flow consists of two parts. First, a scheduler takes a description of a circuit and finds the best order for the execution of its quantum gates using integer linear programming (ILP) regarding the classical resources (qubits) and instruction dependencies. Then a layout generator receives the schedule produced by the scheduler and generates a layout for this circuit using a graph-drawing algorithm. Our experimental results show that the proposed flow decreases the average latency of quantum circuits by about 11% for a set of attempted benchmarks and by about 9% for another set of benchmarks compared with the best in literature.
Abstract The inherent power of quantum computing in parallelizing computations makes it possible to solve some specific problems in a much shorter time than classical computing. Considering the physical issues governing this type of computing, one of the approaches to increase the scalability of such systems is using distributed quantum architectures. A quantum algorithm requires a quantum circuit for a successful implementation. The quantum circuit design flow comprises two main parts: logical synthesis and physical design. Physical synthesis is one of the main steps of the physical design. It improves circuit metrics such as latency and area by changing the netlist or the layout using the information obtained from the initial layout and scheduling. In this paper, we have presented a new physical synthesis method to reduce the quantum circuit delay in distributed architectures. It moves some gates from one partition to another to reduce the number of teleportation operations on the critical path using the scheduled layout information. The experimental results show that this method improves the delay of benchmark circuits on average by 33.40%.
Due to its effect on the success rate of a quantum circuit, quantum layout synthesis is a crucial step for circuit compilation. As such, having a layout synthesis tool that provides high solution quality is important to maximize circuit performance and fidelity for NISQ application. Previous heuristic approaches have been shown to be far from optimal when evaluated on known-optimal benchmarks. Alternatively, exact layout synthesis tools can generate optimal results with the aid of constraint solvers but generally suffer from scalability issues because of inefficient encodings and slow optimization methods. In this paper, we propose a scalable optimal layout synthesis tool that improves upon previous works, through a more succinct problem formulation as well as better encoding techniques. Additionally, we implement a depth and SWAP count optimization feature that performs iterative refinement under a fixed time budget. Experimental results show that for depth optimization, our tool can achieve a 692× speedup over the state-of-the-art optimal layout synthesis, and for SWAP optimization, we can obtain a 6,957× speedup on average. Compared to a leading heuristic-based synthesizer, for depth optimization, we can solve circuits consisting of 54 program qubits and 1726 gates within 11 hours with an 18× depth reduction and by 12× SWAP count reduction on average.
During the physical design process, the second process of the quantum circuit design flow, using some optimization techniques after layout generation might be useful to improve the metrics or meet the design constraints. Focusing on this issue, this paper proposes an optimization technique using gate location changing to improve the latency of quantum circuits. The proposed technique uses layout and scheduling information to find critical paths and improve their latency by changing locations of the gates on the critical paths. Experimental results show that the proposed technique decreases the latency of quantum circuits up to 26% for the attempted benchmarks.
Abstract — Quantum computers are exponentially faster than their classical counterparts in terms of solving some specific, but important problems. The biggest challenge in realizing a quantum computing system is the environmental noise. One way to decrease the effect of noise (and hence, reduce the overhead of building fault tolerant quantum circuits) is to reduce the latency of the quantum circuit that runs on a quantum circuit. In this paper, a novel algorithm is presented for scheduling, placement, and routing of a quantum algorithm, which is to be realized on a target quantum circuit fabric technology. This algorithm, and the accompanying software tool, advances state-of-the-art in quantum CAD methodologies and methods while considering key characteristics and constraints of the ion-trap quantum circuit fabric. Experimental results show that the presented tool improves results of the previous tool by about 41%. Keywords- quantum computing; scheduling; routing; placement; ion-trap technology; CAD tool I.