The assumption of maximum parallelism support for the successful realization of scalable quantum computers has led to homogeneous, "sea-of-qubits" architectures. The resulting architectures overcome the primary challenges of reliability and scalability at the cost of physically unacceptable system area. We find that by exploiting the natural serialization at both the application and the physical microarchitecture level of a quantum computer, we can reduce the area requirement while improving performance. In particular we present a scalable quantum architecture design that employs specialization of the system into memory and computational regions, each individually optimized to match hardware support to the available parallelism. Through careful application and system analysis, we find that our new architecture can yield up to a factor of thirteen savings in area due to specialization. In addition, by providing a memory hierarchy design for quantum computers, we can increase time performance by a factor of eight. This result brings us closer to the realization of a quantum processor that can solve meaningful problems
The assumption of maximum parallelism support for the successful realization of scalable quantum computers has led to homogeneous, "sea-of-qubits" architectures. The resulting architectures overcome the primary challenges of reliability and scalability at the cost of physically unacceptable system area. We find that by exploiting the natural serialization at both the application and the physical microarchitecture level of a quantum computer, we can reduce the area requirement while improving performance. In particular we present a scalable quantum architecture design that employs specialization of the system into memory and computational regions, each individually optimized to match hardware support to the available parallelism. Through careful application and system analysis, we find that our new architecture can yield up to a factor of thirteen savings in area due to specialization. In addition, by providing a memory hierarchy design for quantum computers, we can increase time performance by a factor of eight. This result brings us closer to the realization of a quantum processor that can solve meaningful problems
The assumption of maximum parallelism support for the successful realization of scalable quantum computers has led to homogeneous, "sea-of-qubits" architectures. The resulting architectures overcome the primary challenges of reliability and scalability at the cost of physically unacceptable system area. We find that by exploiting the natural serialization at both the application and the physical microarchitecture level of a quantum computer, we can reduce the area requirement while improving performance. In particular we present a scalable quantum architecture design that employs specialization of the system into memory and computational regions, each individually optimized to match hardware support to the available parallelism. Through careful application and system analysis, we find that our new architecture can yield up to a factor of thirteen savings in area due to specialization. In addition, by providing a memory hierarchy design for quantum computers, we can increase time performance by a factor of eight. This result brings us closer to the realization of a quantum processor that can solve meaningful problems.
Quantum computing is an emerging field that offers revolutionary and exciting new ways to process, store, and transport information. Moreover, realizing large-scale quantum systems requires advances in science and engineering that are now very close to reality. Such systems will need many classical and quantum parts that must fit together into one architecture, in which each component plays an integral role over the course of an application execution. Therefore, it is important that we draw upon the experiences gained from traditional architectures, to develop a model for a large-scale quantum system that provides the methodology necessary for the many different components to work together.
In this thesis, I describe the design of the Quantum Logic Array (QLA) architecture, which tackles critical scalability issues such as the cost of error correction and distributing data over large-distances. To accurately model the performance of the QLA architecture—the ion-trap technology is used since every component necessary for universal quantum computation has been demonstrated in the laboratory. However, due to its design approach for maximizing parallelism, the QLA system suffers from large area overhead. To combat the area problem, I describe an architecture that uses the concept of hardware specialization employed in traditional architectures. The new architecture is based on the QLA model, but is divided into separately optimized quantum memory hierarchy and logic specific regions. The result is a scalable system design that exploits the available parallelism to balance both quantum and classical resources, while both reducing the area of the chip and increasing its performance.
In recent years, quantum computing (QC) research has moved from the realm of theoretical physics and mathematics into real implementations. With many different potential hardware implementations, quantum computer architecture is a rich field with an opportunity to solve interesting new problems and to revisit old ones. This paper presents a QC architecture tailored to physical implementations with highly mobile and persistent quantum bits (qubits). Implementations with qubit coherency times that are much longer than operation times and qubit transportation times that are orders of magnitude faster than operation times lend greater flexibility to the architecture. This is particularly true in the placement and locality of individual qubits. For concreteness, we assume a physical device model based on electron-spin qubits on liquid helium (eSHe). Like many conventional computer architectures, QCs focus on the efficient exposure of parallelism.We present here a QC microarchitecture that enjoys increasing computational parallelism with size and latency scaling only linearly with the number of operations. Although an efficient and high level of parallelism is admirable, quantum hardware is still expensive and difficult to build, so we demonstrate how the software may be optimized to reduce an application's hardware requirements by 25% with no performance loss. Because the majority of a QC's time and resources are devoted to quantum error correction, we also present noise modeling results that evaluate error correction procedures. These results demonstrate that idle qubits in memory need only be refreshedapproximately once every one hundred operation cycles.
Quantum computer hardware is predicted to scale over hundreds of thousands of qubits coming online in the next decade. Despite significant theoretical and experimental QEC progress, quantum computer architecture has suffered a significant gap, with bottom-up physical-device-driven challenges largely disconnected from top-down QEC-code-driven considerations. In this work, we unify these two views, presenting a complete heterogeneous quantum computing architecture incorporating task-specific hardware selection and QEC encoding, and agnostic to code selection or physical qubit parameters. Our approach further enables special-purpose processing modules, and includes a full microarchitecture for fault-tolerant implementation of interfaces between quantum processing units and quantum memories. Using this architecture and a new fully featured compiler functioning across subsystems at the scale of 1,000 logical qubits, we schedule and orchestrate a variety of algorithms down to hardware-specific instructions; a detailed accounting of all operations reveals up to 551x reduction in algorithmic logical error and up to 138x reduction in physical-qubit overhead compared to a monolithic baseline architecture. We then consider the factorization of 2048-bit RSA-integers; using an experimentally demonstrated grid-coupling topology, factoring RSA-2048 requires 381k physical qubits and 9.2 days, which can be reduced to 4.9 days via addition of an algorithm-specific accelerator for the Adder subroutine (requiring 439k qubits). Finally, assuming hypothetical long-range coupling, implementing quantum memory using qLDPC codes reduces the resources required for factoring to just 190k qubits and under 10 days. These results and the tooling we have built indicate that heterogeneous quantum-computer architectures can deliver significant, verifiable benefits on realistic hardware.
This thesis addresses the design of a quantum computer (QC) architecture. Quantum error correction is a dominant factor as it is required to protect quantum bits (qubits) from decoherence. However, error correction's costs are substantial and call for a scale-up of 100X more qubits and instruction-level parallelism (ILP) on the order of 10,000 simultaneous operations per cycle. These are daunting challenges for a QC architect, who must balance demands in performance, control efficiency, and scalability of design.
Error modeling is important for designing a QC so that error correction implementations and microarchitecture designs may be evaluated for effectiveness. This thesis presents a new deterministic approach to error modeling that is on the order of 1000X faster than previous Monte Carlo error models. While the deterministic error model is memory limited, it is capable of evaluating useful problems containing on the order of a dozen logical qubits encoded in the [[7,1,3]] quantum error correcting code (QECC).
This dissertation presents a new QC processor architecture that leverages highly mobile qubits found in some QC technologies such as electron-spins on liquid helium (eSHe). The processor architecture presented here is designed to efficiently handle at least an order of magnitude more ILP than previously proposed designs, and it accommodates increasing ILP with size and latency costs scaling only linearly. Compilers are also crucial to a computer's performance and efficiency, and this dissertation describes new compiler optimizations including one that reduces hardware requirements by 25% with no performance loss.
Multiple QC processors may be organized into a tiled configuration to provide sufficient ILP across the entire QC. This dissertation proposes a new distributed block tiling strategy that distributes encoded block qubits across arrays of data tiles and offloads non-critical path error correction routines to separate ancilla tiles. This strategy reduces tile capacity requirements by over 100X with the [[21,3,5]] QECC and achieves a simulated speedup of 2.8X for the eSHe QC when compared to the traditional tiling approach.
In summary, this dissertation presents a novel QC architecture and design tools that improve performance and scalability while making efficient use of both control and qubit resources.
Scaling bottlenecks the making of digital quantum computers, posing challenges from both the quantum and the classical components. We present a classical architecture to cope with a comprehensive list of the latter challenges all at once , and implement it fully in an end-to-end system by integrating a multi-core RISC-V CPU with our in-house control electronics. Our architecture enables scalable, high-precision control of large quantum processors and accommodates evolving requirements of quantum hardware. A central feature is a microarchitecture executing quantum operations in parallel on arbitrary predefined qubit groups. Another key feature is a reconfigurable quantum instruction set that supports easy qubit re-grouping and instructions extensions. As a demonstration, we implement the widely-studied surface code quantum computing workflow, which is instructive for being demanding on both the controllers and the integrated classical computation. Our design, for the first time, reduces instruction issuing and transmission costs to constants, which do not scale with the number of qubits, without adding any overheads in decoding or dispatching. Our system uses a dedicated general-purpose CPU for both qubit control and classical computation, including syndrome decoding. Implementing recent theoretical proposals as decoding firmware that parallelizes general inner decoders, we can achieve unprecedented decoding capabilities of up to distances 47 and 67 with the currently available systems-on-chips for physical error rate p = 0.001 and p = 0.0001, respectively, all in just 1 μs.