This thesis addresses the design of a quantum computer (QC) architecture. Quantum error correction is a dominant factor as it is required to protect quantum bits (qubits) from decoherence. However, error correction's costs are substantial and call for a scale-up of 100X more qubits and instruction-level parallelism (ILP) on the order of 10,000 simultaneous operations per cycle. These are daunting challenges for a QC architect, who must balance demands in performance, control efficiency, and scalability of design.
Error modeling is important for designing a QC so that error correction implementations and microarchitecture designs may be evaluated for effectiveness. This thesis presents a new deterministic approach to error modeling that is on the order of 1000X faster than previous Monte Carlo error models. While the deterministic error model is memory limited, it is capable of evaluating useful problems containing on the order of a dozen logical qubits encoded in the [[7,1,3]] quantum error correcting code (QECC).
This dissertation presents a new QC processor architecture that leverages highly mobile qubits found in some QC technologies such as electron-spins on liquid helium (eSHe). The processor architecture presented here is designed to efficiently handle at least an order of magnitude more ILP than previously proposed designs, and it accommodates increasing ILP with size and latency costs scaling only linearly. Compilers are also crucial to a computer's performance and efficiency, and this dissertation describes new compiler optimizations including one that reduces hardware requirements by 25% with no performance loss.
Multiple QC processors may be organized into a tiled configuration to provide sufficient ILP across the entire QC. This dissertation proposes a new distributed block tiling strategy that distributes encoded block qubits across arrays of data tiles and offloads non-critical path error correction routines to separate ancilla tiles. This strategy reduces tile capacity requirements by over 100X with the [[21,3,5]] QECC and achieves a simulated speedup of 2.8X for the eSHe QC when compared to the traditional tiling approach.
In summary, this dissertation presents a novel QC architecture and design tools that improve performance and scalability while making efficient use of both control and qubit resources.
This thesis addresses the design of a quantum computer (QC) architecture. Quantum error correction is a dominant factor as it is required to protect quantum bits (qubits) from decoherence. However, error correction's costs are substantial and call for a scale-up of 100X more qubits and instruction-level parallelism (ILP) on the order of 10,000 simultaneous operations per cycle. These are daunting challenges for a QC architect, who must balance demands in performance, control efficiency, and scalability of design.
Error modeling is important for designing a QC so that error correction implementations and microarchitecture designs may be evaluated for effectiveness. This thesis presents a new deterministic approach to error modeling that is on the order of 1000X faster than previous Monte Carlo error models. While the deterministic error model is memory limited, it is capable of evaluating useful problems containing on the order of a dozen logical qubits encoded in the [[7,1,3]] quantum error correcting code (QECC).
This dissertation presents a new QC processor architecture that leverages highly mobile qubits found in some QC technologies such as electron-spins on liquid helium (eSHe). The processor architecture presented here is designed to efficiently handle at least an order of magnitude more ILP than previously proposed designs, and it accommodates increasing ILP with size and latency costs scaling only linearly. Compilers are also crucial to a computer's performance and efficiency, and this dissertation describes new compiler optimizations including one that reduces hardware requirements by 25% with no performance loss.
Multiple QC processors may be organized into a tiled configuration to provide sufficient ILP across the entire QC. This dissertation proposes a new distributed block tiling strategy that distributes encoded block qubits across arrays of data tiles and offloads non-critical path error correction routines to separate ancilla tiles. This strategy reduces tile capacity requirements by over 100X with the [[21,3,5]] QECC and achieves a simulated speedup of 2.8X for the eSHe QC when compared to the traditional tiling approach.
In summary, this dissertation presents a novel QC architecture and design tools that improve performance and scalability while making efficient use of both control and qubit resources.
In recent years, quantum computing (QC) research has moved from the realm of theoretical physics and mathematics into real implementations. With many different potential hardware implementations, quantum computer architecture is a rich field with an opportunity to solve interesting new problems and to revisit old ones. This paper presents a QC architecture tailored to physical implementations with highly mobile and persistent quantum bits (qubits). Implementations with qubit coherency times that are much longer than operation times and qubit transportation times that are orders of magnitude faster than operation times lend greater flexibility to the architecture. This is particularly true in the placement and locality of individual qubits. For concreteness, we assume a physical device model based on electron-spin qubits on liquid helium (eSHe). Like many conventional computer architectures, QCs focus on the efficient exposure of parallelism.We present here a QC microarchitecture that enjoys increasing computational parallelism with size and latency scaling only linearly with the number of operations. Although an efficient and high level of parallelism is admirable, quantum hardware is still expensive and difficult to build, so we demonstrate how the software may be optimized to reduce an application's hardware requirements by 25% with no performance loss. Because the majority of a QC's time and resources are devoted to quantum error correction, we also present noise modeling results that evaluate error correction procedures. These results demonstrate that idle qubits in memory need only be refreshedapproximately once every one hundred operation cycles.
Quantum computing is an emerging field that offers revolutionary and exciting new ways to process, store, and transport information. Moreover, realizing large-scale quantum systems requires advances in science and engineering that are now very close to reality. Such systems will need many classical and quantum parts that must fit together into one architecture, in which each component plays an integral role over the course of an application execution. Therefore, it is important that we draw upon the experiences gained from traditional architectures, to develop a model for a large-scale quantum system that provides the methodology necessary for the many different components to work together.
In this thesis, I describe the design of the Quantum Logic Array (QLA) architecture, which tackles critical scalability issues such as the cost of error correction and distributing data over large-distances. To accurately model the performance of the QLA architecture—the ion-trap technology is used since every component necessary for universal quantum computation has been demonstrated in the laboratory. However, due to its design approach for maximizing parallelism, the QLA system suffers from large area overhead. To combat the area problem, I describe an architecture that uses the concept of hardware specialization employed in traditional architectures. The new architecture is based on the QLA model, but is divided into separately optimized quantum memory hierarchy and logic specific regions. The result is a scalable system design that exploits the available parallelism to balance both quantum and classical resources, while both reducing the area of the chip and increasing its performance.
Quantum computing is positioned to be a transformative technology to key areas of scientific interest such as quantum chemistry, material science, and cryptography. At a hardware level, recent years have seen broad progress in a variety of qubit modalities, however, error rates are still orders of magnitude higher than what is necessary for large-scale quantum programs. This gap in error rates motivates the use of quantum error correction (QEC) and the realization of fault-tolerant quantum computing (FTQC), yet today, although the theory of FTQC is promising, effectively connecting it to real devices poses significant challenges. In this dissertation we study opportunities for more efficient and scalable FTQC architectures through the co-design of quantum hardware and software. We first look at how unique hardware capabilities in quantum computers made from 2D arrays of optically trapped atoms can improve QEC performance. For computation, we study how longer-range interactions between atoms can enable a novel embedding of QEC blocks on physical qubits that improves logical-level connectivity. For memory, we study how mid-circuit movement of atoms can effectively implement higher encoding rate QEC codes, creating a qubit-efficient memory system. We next consider the performance impact of real-time classical systems in FTQC architectures, and explore the use of speculation to improve large-scale decoding systems. Finally, we study how software systems can be used to improve QEC designs. We consider the problem of QEC circuit optimization, and study an automated approach based on iterative optimization of performance-reducing subcircuits.
Quantum bits have technological imperfections.Additionally, the capacity of a component that can be implemented feasibly is limited.Therefore, distributed quantum computation is required to scale up quantum computers able to solve usefully large problems.This dissertation presents the design of components of quantum CPUs and of quantum memories taking into account imperfections.Quantum CPUs employ a quantum error correcting code which has faster logical gates and quantum memories employ a code which is superior in space resource requirements.This new quantum computer architecture aimed to realize distributed computation by connecting quantum computer each of which consists of multiple quantum CPUs and multiple quantum memories.This dissertation focuses on quantum error correcting codes, giving a practical, concrete method for tolerating static losses such as faulty devices for the surface code.To validate this method, I analyzed the resource consumption of cases where faulty devices exist and quantified the increase of resource consumption by numerical simulation with practical assumptions.I found that a yield of functional qubits of 90% is marginally capable of building large-scale systems, by culling the poorer 50% of chips during postfabrication testing.Yield 80% is not usable even when discarding 90% of generated lattices.For the internal connections between quantum CPU and memory components in a quantum computer and for connections of quantum computers, this dissertation gives a fault-tolerant method to connect quantum components that employ heterogeneous quantum error correcting codes.I have validated this method and quantified the resource consumption of the error management by numerical simulation.I found that the scheme, which discards any quantum state in which any error is detected, always achieves an adequate logical error rate regardless of physical error rates in exchange for increased resource consumption.ii iii Additionally, this dissertation gives a new extension of the surface code suitable for quantum memories.This code is shown to require fewer physical qubits to encode a logical qubit than conventional codes.This code achieves the reduction of 50% physical qubits per a logical qubit.Collectively, the elements to construct distributed quantum computation by connecting quantum computers are brought together to propose a distributed quantum computer architecture.
The transition from noisy intermediate-scale quantum (NISQ) processors to large-scale fault-tolerant machines requires more than incremental improvements in physical qubit fidelity. While advances in quantum error correction (QEC) theory continue to lower the theoretical overhead of quantum computing, much of this research remains abstracted from the physical realities of qubit implementations. This disconnect often results in hardware-agnostic designs that are inefficient or impractical to build. In this dissertation, I identify three primary gaps between theoretical QEC research and practical hardware: (1) the high levels of noise and temporal instability in experimental devices that impede scalable QEC; (2) the prohibitively large qubit and time costs of useful algorithms, driven largely by the limitations of the standard surface code; and (3) the failure of current resource estimates to account for hardware-level constraints, such as limited connectivity and the complexity of implementing non-local operations. To bridge these gaps, I propose a holistic, cross-stack approach where the error correction protocols and the physical hardware are designed in concert. By developing realistic device models and hardware-aware solutions at the lowest levels of the software stack, we can accelerate the path toward functional fault-tolerance. I present my work across three research thrusts: first, leveraging codesign to mitigate hardware-specific noise and reduce physical error rates; second, developing software tools for fault-tolerant quantum computers to reduce the space-time overhead of the QEC layer; and third, proposing two novel hardware-aware QEC architectures that provide practical, high-performance routes to scalable quantum computation.
Quantum computing may solve selected classes of problems more efficiently than classical computers, with applications in areas such as cryptography, chemistry, and optimization. However, current quantum systems remain limited in scale and reliability and depend on substantial classical-computing support. This thesis investigates this challenge in two complementary contexts: classical simulation, where efficient computation enables the exploration of larger quantum systems; and quantum error correction, where efficient real-time decoding enables more reliable quantum operation.The first part examines the classical simulation of quantum computers, focusing on the computational and memory challenges that limit its scalability. It organizes the field across device, gate, and algorithmic levels, with particular attention to state-vector, path-based, hybrid, and tensor-based methods. The survey relates their computation, memory, data-movement, and communication bottlenecks to acceleration approaches for CPUs, GPUs, FPGAs, and distributed systems. It further highlights recurring optimization strategies, including reduced precision, data compression, parallel execution, improved memory locality, specialized matrix units, and reconfigurable hardware, providing a common framework for current techniques and future acceleration opportunities.The second part addresses the real-time classical processing required for quantum error correction. Starting from a high-accuracy Graph Neural Network surface-code decoder, it applies algorithm-hardware co-design through hardware-guided pruning and retraining, input-graph filtering, quantization, and a custom FPGA architecture. For code distances up to d=7, the resulting designs satisfy both max-latency and average-latency decoding requirements while reducing the logical error rate by 13% and 40%, respectively, compared with the evaluated Minimum Weight Perfect Matching baseline.Together, these works show how classical computer-architecture techniques can support quantum computing from scalable exploration through simulation to reliable operation through real-time error correction.