Quantum bits have technological imperfections.Additionally, the capacity of a component that can be implemented feasibly is limited.Therefore, distributed quantum computation is required to scale up quantum computers able to solve usefully large problems.This dissertation presents the design of components of quantum CPUs and of quantum memories taking into account imperfections.Quantum CPUs employ a quantum error correcting code which has faster logical gates and quantum memories employ a code which is superior in space resource requirements.This new quantum computer architecture aimed to realize distributed computation by connecting quantum computer each of which consists of multiple quantum CPUs and multiple quantum memories.This dissertation focuses on quantum error correcting codes, giving a practical, concrete method for tolerating static losses such as faulty devices for the surface code.To validate this method, I analyzed the resource consumption of cases where faulty devices exist and quantified the increase of resource consumption by numerical simulation with practical assumptions.I found that a yield of functional qubits of 90% is marginally capable of building large-scale systems, by culling the poorer 50% of chips during postfabrication testing.Yield 80% is not usable even when discarding 90% of generated lattices.For the internal connections between quantum CPU and memory components in a quantum computer and for connections of quantum computers, this dissertation gives a fault-tolerant method to connect quantum components that employ heterogeneous quantum error correcting codes.I have validated this method and quantified the resource consumption of the error management by numerical simulation.I found that the scheme, which discards any quantum state in which any error is detected, always achieves an adequate logical error rate regardless of physical error rates in exchange for increased resource consumption.ii iii Additionally, this dissertation gives a new extension of the surface code suitable for quantum memories.This code is shown to require fewer physical qubits to encode a logical qubit than conventional codes.This code achieves the reduction of 50% physical qubits per a logical qubit.Collectively, the elements to construct distributed quantum computation by connecting quantum computers are brought together to propose a distributed quantum computer architecture.
Quantum bits have technological imperfections.Additionally, the capacity of a component that can be implemented feasibly is limited.Therefore, distributed quantum computation is required to scale up quantum computers able to solve usefully large problems.This dissertation presents the design of components of quantum CPUs and of quantum memories taking into account imperfections.Quantum CPUs employ a quantum error correcting code which has faster logical gates and quantum memories employ a code which is superior in space resource requirements.This new quantum computer architecture aimed to realize distributed computation by connecting quantum computer each of which consists of multiple quantum CPUs and multiple quantum memories.This dissertation focuses on quantum error correcting codes, giving a practical, concrete method for tolerating static losses such as faulty devices for the surface code.To validate this method, I analyzed the resource consumption of cases where faulty devices exist and quantified the increase of resource consumption by numerical simulation with practical assumptions.I found that a yield of functional qubits of 90% is marginally capable of building large-scale systems, by culling the poorer 50% of chips during postfabrication testing.Yield 80% is not usable even when discarding 90% of generated lattices.For the internal connections between quantum CPU and memory components in a quantum computer and for connections of quantum computers, this dissertation gives a fault-tolerant method to connect quantum components that employ heterogeneous quantum error correcting codes.I have validated this method and quantified the resource consumption of the error management by numerical simulation.I found that the scheme, which discards any quantum state in which any error is detected, always achieves an adequate logical error rate regardless of physical error rates in exchange for increased resource consumption.ii iii Additionally, this dissertation gives a new extension of the surface code suitable for quantum memories.This code is shown to require fewer physical qubits to encode a logical qubit than conventional codes.This code achieves the reduction of 50% physical qubits per a logical qubit.Collectively, the elements to construct distributed quantum computation by connecting quantum computers are brought together to propose a distributed quantum computer architecture.
Quantum bits have technological imperfections. Additionally, the capacity of a component that can be implemented feasibly is limited. Therefore, distributed quantum computation is required to scale up quantum computers. This dissertation presents a new quantum computer architecture which takes into account imperfections, aimed to realize distributed computation by connecting quantum computers each of which consists of multiple quantum CPUs and memories. Quantum CPUs employ a quantum error correcting code which has faster logical gates and quantum memories employ a code which is superior in space resource requirements. This dissertation focuses on quantum error correcting codes, giving a practical, concrete method for tolerating static losses such as faulty devices for the surface code. Numerical simulation with practical assumptions showed that a yield of functional qubits of 90% is marginally capable of building large-scale systems, by culling the poorer 50% of lattices during post-fabrication testing. Yield 80% is not usable even when culling 90% of generated lattices. For internal connections in a quantum computer and for connections between quantum computers, this dissertation gives a fault-tolerant method that bridges heterogeneous quantum error correcting codes. Numerical simulation showed that the scheme, which discards any quantum state in which any error is detected, always achieves an adequate logical error rate regardless of physical error rates in exchange for increased resource consumption. This dissertation gives a new extension of the surface code suitable for memories. This code is shown to require fewer physical qubits to encode a logical qubit than conventional codes. This code achieves the reduction of 50% physical qubits per a logical qubit. Collectively, the elements to propose the distributed quantum computer architecture are brought together.
The limited qubit resources of current quantum processing units (QPUs), together with their susceptibility to operational imperfections, environmental noise, and error propagation, not only degrade computational fidelity but also constrain the scalability required for utility-scale quantum computing. Consequently, the transition from monolithic architectures to distributed quantum computing (DQC), supported by distributed quantum error-correcting codes (QECCs), is emerging as a promising paradigm for large-scale fault-tolerant quantum computing (FTQC). This transition represents a full-stack challenge that requires coordinated advances in quantum architecture, fault-tolerant gate operations, and classical–quantum co-processing and control. In this paper, we review the theoretical foundations and practical realization of large-scale FTQC. We first explore major families of QECCs, including topological, qLDPC, subsystem, and dynamical codes, with emphasis on code construction, syndrome extraction, and decoding. We then review the implementation of fault-tolerant universal gate sets at the physical and logical levels, followed by entanglement generation, distribution, and purification for distributed architectures. Finally, we outline open challenges and future research directions in theory, architecture, and implementation, highlighting the role of distributed fault-tolerant designs in next-generation utility-scale quantum computing.
This thesis addresses the design of a quantum computer (QC) architecture. Quantum error correction is a dominant factor as it is required to protect quantum bits (qubits) from decoherence. However, error correction's costs are substantial and call for a scale-up of 100X more qubits and instruction-level parallelism (ILP) on the order of 10,000 simultaneous operations per cycle. These are daunting challenges for a QC architect, who must balance demands in performance, control efficiency, and scalability of design.
Error modeling is important for designing a QC so that error correction implementations and microarchitecture designs may be evaluated for effectiveness. This thesis presents a new deterministic approach to error modeling that is on the order of 1000X faster than previous Monte Carlo error models. While the deterministic error model is memory limited, it is capable of evaluating useful problems containing on the order of a dozen logical qubits encoded in the [[7,1,3]] quantum error correcting code (QECC).
This dissertation presents a new QC processor architecture that leverages highly mobile qubits found in some QC technologies such as electron-spins on liquid helium (eSHe). The processor architecture presented here is designed to efficiently handle at least an order of magnitude more ILP than previously proposed designs, and it accommodates increasing ILP with size and latency costs scaling only linearly. Compilers are also crucial to a computer's performance and efficiency, and this dissertation describes new compiler optimizations including one that reduces hardware requirements by 25% with no performance loss.
Multiple QC processors may be organized into a tiled configuration to provide sufficient ILP across the entire QC. This dissertation proposes a new distributed block tiling strategy that distributes encoded block qubits across arrays of data tiles and offloads non-critical path error correction routines to separate ancilla tiles. This strategy reduces tile capacity requirements by over 100X with the [[21,3,5]] QECC and achieves a simulated speedup of 2.8X for the eSHe QC when compared to the traditional tiling approach.
In summary, this dissertation presents a novel QC architecture and design tools that improve performance and scalability while making efficient use of both control and qubit resources.
Fault tolerant quantum computation over distributed quantum computing (DQC) platforms requires careful evaluation of resource requirements and noise thresholds. As quantum hardware advances toward modular and networked architectures, various fault tolerant DQC schemes have been proposed, which can be broadly categorized into three architectural types. Type 1 architectures consist of small quantum nodes connected via Greenberger-Horne-Zeilinger (GHZ) states, enabling nonlocal stabilizer measurements. Type 2 architectures distribute a large error correcting code block across multiple modules, with most stabilizer measurements remaining local, except for a small subset at patch boundaries that are performed using nonlocal CNOT gates. Type 3 architectures assign code blocks to distinct modules and can perform fault tolerant operations such as transversal gates, lattice surgery, and teleportation to implement logical operations between code blocks. Using the planar surface code and toric code as representative examples, we analyze how the resource requirements, particularly the number of Bell pairs and the average number of generation attempts, scale with increasing code distance across different architectural designs. This analysis provides valuable insights for identifying architectures well suited to fault tolerant distributed quantum computation under near term hardware and resource constraints.
Quantum computing is positioned to be a transformative technology to key areas of scientific interest such as quantum chemistry, material science, and cryptography. At a hardware level, recent years have seen broad progress in a variety of qubit modalities, however, error rates are still orders of magnitude higher than what is necessary for large-scale quantum programs. This gap in error rates motivates the use of quantum error correction (QEC) and the realization of fault-tolerant quantum computing (FTQC), yet today, although the theory of FTQC is promising, effectively connecting it to real devices poses significant challenges. In this dissertation we study opportunities for more efficient and scalable FTQC architectures through the co-design of quantum hardware and software. We first look at how unique hardware capabilities in quantum computers made from 2D arrays of optically trapped atoms can improve QEC performance. For computation, we study how longer-range interactions between atoms can enable a novel embedding of QEC blocks on physical qubits that improves logical-level connectivity. For memory, we study how mid-circuit movement of atoms can effectively implement higher encoding rate QEC codes, creating a qubit-efficient memory system. We next consider the performance impact of real-time classical systems in FTQC architectures, and explore the use of speculation to improve large-scale decoding systems. Finally, we study how software systems can be used to improve QEC designs. We consider the problem of QEC circuit optimization, and study an automated approach based on iterative optimization of performance-reducing subcircuits.
Abstract Connecting multiple smaller qubit modules by generating high-fidelity entanglement is a promising path for scaling quantum computing hardware. The performance of such a modular quantum computer depends on the quality and rate of entanglement generation. However, identifying optimal architectures and entanglement generation protocols remains an open question. How can modular quantum architectures be designed to achieve fault tolerance while requiring only feasible entanglement rates and hardware? Focusing on solid-state quantum hardware, we investigate the threshold and logical failure rate of a fully distributed surface code. We consider both emission-based and scattering-based entanglement schemes between the modules to link the performance to the physical hardware and identify the regime for fault tolerance. We compare architectures with one or two data qubits per module. For some entanglement schemes, thresholds nearing the thresholds of non-distributed implementations (~ 0.4%) appear feasible with future parameters minimizing the performance gap between modular and monolithic quantum processors.