Quantum bits have technological imperfections. Additionally, the capacity of a component that can be implemented feasibly is limited. Therefore, distributed quantum computation is required to scale up quantum computers. This dissertation presents a new quantum computer architecture which takes into account imperfections, aimed to realize distributed computation by connecting quantum computers each of which consists of multiple quantum CPUs and memories. Quantum CPUs employ a quantum error correcting code which has faster logical gates and quantum memories employ a code which is superior in space resource requirements. This dissertation focuses on quantum error correcting codes, giving a practical, concrete method for tolerating static losses such as faulty devices for the surface code. Numerical simulation with practical assumptions showed that a yield of functional qubits of 90% is marginally capable of building large-scale systems, by culling the poorer 50% of lattices during post-fabrication testing. Yield 80% is not usable even when culling 90% of generated lattices. For internal connections in a quantum computer and for connections between quantum computers, this dissertation gives a fault-tolerant method that bridges heterogeneous quantum error correcting codes. Numerical simulation showed that the scheme, which discards any quantum state in which any error is detected, always achieves an adequate logical error rate regardless of physical error rates in exchange for increased resource consumption. This dissertation gives a new extension of the surface code suitable for memories. This code is shown to require fewer physical qubits to encode a logical qubit than conventional codes. This code achieves the reduction of 50% physical qubits per a logical qubit. Collectively, the elements to propose the distributed quantum computer architecture are brought together.
Quantum bits have technological imperfections. Additionally, the capacity of a component that can be implemented feasibly is limited. Therefore, distributed quantum computation is required to scale up quantum computers. This dissertation presents a new quantum computer architecture which takes into account imperfections, aimed to realize distributed computation by connecting quantum computers each of which consists of multiple quantum CPUs and memories. Quantum CPUs employ a quantum error correcting code which has faster logical gates and quantum memories employ a code which is superior in space resource requirements. This dissertation focuses on quantum error correcting codes, giving a practical, concrete method for tolerating static losses such as faulty devices for the surface code. Numerical simulation with practical assumptions showed that a yield of functional qubits of 90% is marginally capable of building large-scale systems, by culling the poorer 50% of lattices during post-fabrication testing. Yield 80% is not usable even when culling 90% of generated lattices. For internal connections in a quantum computer and for connections between quantum computers, this dissertation gives a fault-tolerant method that bridges heterogeneous quantum error correcting codes. Numerical simulation showed that the scheme, which discards any quantum state in which any error is detected, always achieves an adequate logical error rate regardless of physical error rates in exchange for increased resource consumption. This dissertation gives a new extension of the surface code suitable for memories. This code is shown to require fewer physical qubits to encode a logical qubit than conventional codes. This code achieves the reduction of 50% physical qubits per a logical qubit. Collectively, the elements to propose the distributed quantum computer architecture are brought together.
Quantum bits have technological imperfections.Additionally, the capacity of a component that can be implemented feasibly is limited.Therefore, distributed quantum computation is required to scale up quantum computers able to solve usefully large problems.This dissertation presents the design of components of quantum CPUs and of quantum memories taking into account imperfections.Quantum CPUs employ a quantum error correcting code which has faster logical gates and quantum memories employ a code which is superior in space resource requirements.This new quantum computer architecture aimed to realize distributed computation by connecting quantum computer each of which consists of multiple quantum CPUs and multiple quantum memories.This dissertation focuses on quantum error correcting codes, giving a practical, concrete method for tolerating static losses such as faulty devices for the surface code.To validate this method, I analyzed the resource consumption of cases where faulty devices exist and quantified the increase of resource consumption by numerical simulation with practical assumptions.I found that a yield of functional qubits of 90% is marginally capable of building large-scale systems, by culling the poorer 50% of chips during postfabrication testing.Yield 80% is not usable even when discarding 90% of generated lattices.For the internal connections between quantum CPU and memory components in a quantum computer and for connections of quantum computers, this dissertation gives a fault-tolerant method to connect quantum components that employ heterogeneous quantum error correcting codes.I have validated this method and quantified the resource consumption of the error management by numerical simulation.I found that the scheme, which discards any quantum state in which any error is detected, always achieves an adequate logical error rate regardless of physical error rates in exchange for increased resource consumption.ii iii Additionally, this dissertation gives a new extension of the surface code suitable for quantum memories.This code is shown to require fewer physical qubits to encode a logical qubit than conventional codes.This code achieves the reduction of 50% physical qubits per a logical qubit.Collectively, the elements to construct distributed quantum computation by connecting quantum computers are brought together to propose a distributed quantum computer architecture.
Fault tolerant quantum computation over distributed quantum computing (DQC) platforms requires careful evaluation of resource requirements and noise thresholds. As quantum hardware advances toward modular and networked architectures, various fault tolerant DQC schemes have been proposed, which can be broadly categorized into three architectural types. Type 1 architectures consist of small quantum nodes connected via Greenberger-Horne-Zeilinger (GHZ) states, enabling nonlocal stabilizer measurements. Type 2 architectures distribute a large error correcting code block across multiple modules, with most stabilizer measurements remaining local, except for a small subset at patch boundaries that are performed using nonlocal CNOT gates. Type 3 architectures assign code blocks to distinct modules and can perform fault tolerant operations such as transversal gates, lattice surgery, and teleportation to implement logical operations between code blocks. Using the planar surface code and toric code as representative examples, we analyze how the resource requirements, particularly the number of Bell pairs and the average number of generation attempts, scale with increasing code distance across different architectural designs. This analysis provides valuable insights for identifying architectures well suited to fault tolerant distributed quantum computation under near term hardware and resource constraints.
The limited qubit resources of current quantum processing units (QPUs), together with their susceptibility to operational imperfections, environmental noise, and error propagation, not only degrade computational fidelity but also constrain the scalability required for utility-scale quantum computing. Consequently, the transition from monolithic architectures to distributed quantum computing (DQC), supported by distributed quantum error-correcting codes (QECCs), is emerging as a promising paradigm for large-scale fault-tolerant quantum computing (FTQC). This transition represents a full-stack challenge that requires coordinated advances in quantum architecture, fault-tolerant gate operations, and classical–quantum co-processing and control. In this paper, we review the theoretical foundations and practical realization of large-scale FTQC. We first explore major families of QECCs, including topological, qLDPC, subsystem, and dynamical codes, with emphasis on code construction, syndrome extraction, and decoding. We then review the implementation of fault-tolerant universal gate sets at the physical and logical levels, followed by entanglement generation, distribution, and purification for distributed architectures. Finally, we outline open challenges and future research directions in theory, architecture, and implementation, highlighting the role of distributed fault-tolerant designs in next-generation utility-scale quantum computing.
Building fault-tolerant quantum computers with large numbers of logical qubits requires both scalable hardware architectures and error-correcting codes that make efficient use of physical qubits. Photonic interconnects address both of these challenges by allowing the physical qubits to be distributed across multiple processors while providing the non-local connectivity necessary to implement resource-efficient codes such as high-rate quantum low-density parity-check (qLDPC) codes. A key requirement for realising this architecture is the ability to perform stabiliser measurements between remote processors, which has not previously been demonstrated experimentally. Here we report the first experimental demonstration of distributed quantum error detection and correction. We generate entanglement between network qubits in two separate trapped-ion processors and use it to perform remote syndrome measurements on data qubits. We first realise a distributed [[2, 1, 1]] repetition code, detecting phase-flip errors on a logical qubit encoded across the two modules in real time and suppressing logical errors. We then combine these mid-circuit syndrome measurements with real-time feedforward to actively correct arbitrary single-qubit Pauli errors on a distributed Bell state. These results provide an experimental foundation for quantum error correction (QEC) across modular quantum architectures.
Abstract Connecting multiple smaller qubit modules by generating high-fidelity entanglement is a promising path for scaling quantum computing hardware. The performance of such a modular quantum computer depends on the quality and rate of entanglement generation. However, identifying optimal architectures and entanglement generation protocols remains an open question. How can modular quantum architectures be designed to achieve fault tolerance while requiring only feasible entanglement rates and hardware? Focusing on solid-state quantum hardware, we investigate the threshold and logical failure rate of a fully distributed surface code. We consider both emission-based and scattering-based entanglement schemes between the modules to link the performance to the physical hardware and identify the regime for fault tolerance. We compare architectures with one or two data qubits per module. For some entanglement schemes, thresholds nearing the thresholds of non-distributed implementations (~ 0.4%) appear feasible with future parameters minimizing the performance gap between modular and monolithic quantum processors.
Physical constraints and engineering challenges, including wafer dimensions, classical control cabling, and refrigeration volumes, impose significant limitations on the scalability of quantum computing units. As a result, a modular quantum computing architecture, comprising small processors interconnected by quantum links, is emerging as a promising approach to fault-tolerant quantum computing. However, the requirements that the network must fulfill to enable distributed quantum computation remain largely unexplored. We consider an architecture tailored for qubits with nearest-neighbor physical connectivity, leveraging the surface code for error correction and enabling fault-tolerant operations through lattice surgery and magic state distillation. We propose measurement teleportation as a tool to extend lattice surgery techniques to qubits located on different computing units interconnected via Bell pairs. Through memory simulations, we build an error model for logical operations and deduce an end-to-end resource estimation of Shor’s algorithm over a minimalist distributed architecture. Concretely, for a characteristic physical gate error rate of 10 − 3 , a processor cycle time of 1 µs, factoring a 2048-bit RSA integer is shown to be possible with 379 computing processors, each made with 89 781 qubits, with negligible space and time overhead with respect to a monolithic approach without parallelization, if 70 Bell pairs are available per cycle time between each processor with a fidelity exceeding 98.1 % .