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arXiv:2504.08891 · Physical Review Research

Network requirements for distributed quantum computation

Hugo Jacinto, Élie Gouzien, Nicolas Sangouard

Published Jan 9, 2026• 1 citation
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Abstract

Physical constraints and engineering challenges, including wafer dimensions, classical control cabling, and refrigeration volumes, impose significant limitations on the scalability of quantum computing units. As a result, a modular quantum computing architecture, comprising small processors interconnected by quantum links, is emerging as a promising approach to fault-tolerant quantum computing. However, the requirements that the network must fulfill to enable distributed quantum computation remain largely unexplored. We consider an architecture tailored for qubits with nearest-neighbor physical connectivity, leveraging the surface code for error correction and enabling fault-tolerant operations through lattice surgery and magic state distillation. We propose measurement teleportation as a tool to extend lattice surgery techniques to qubits located on different computing units interconnected via Bell pairs. Through memory simulations, we build an error model for logical operations and deduce an end-to-end resource estimation of Shor’s algorithm over a minimalist distributed architecture. Concretely, for a characteristic physical gate error rate of 10 − 3 , a processor cycle time of 1 µs, factoring a 2048-bit RSA integer is shown to be possible with 379 computing processors, each made with 89 781 qubits, with negligible space and time overhead with respect to a monolithic approach without parallelization, if 70 Bell pairs are available per cycle time between each processor with a fidelity exceeding 98.1 % .

DOI
10.1103/v9ln-c4v2

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Physical constraints and engineering challenges, including wafer dimensions, classical control cabling, and refrigeration volumes, impose significant limitations on the scalability of quantum computing units. As a result, a modular quantum computing architecture, comprising small processors interconnected by quantum links, is emerging as a promising approach to fault-tolerant quantum computing. However, the requirements that the network must fulfill to enable distributed quantum computation remain largely unexplored. We consider an architecture tailored for qubits with nearest-neighbor physical connectivity, leveraging the surface code for error correction and enabling fault-tolerant operations through lattice surgery and magic state distillation. We propose measurement teleportation as a tool to extend lattice surgery techniques to qubits located on different computing units interconnected via Bell pairs. Through memory simulations, we build an error model for logical operations and deduce an end-to-end resource estimation of Shor’s algorithm over a minimalist distributed architecture. Concretely, for a characteristic physical gate error rate of 10 − 3 , a processor cycle time of 1 µs, factoring a 2048-bit RSA integer is shown to be possible with 379 computing processors, each made with 89 781 qubits, with negligible space and time overhead with respect to a monolithic approach without parallelization, if 70 Bell pairs are available per cycle time between each processor with a fidelity exceeding 98.1 % .
Modular architectures are a promising approach to scaling quantum computers to fault tolerance. Small, low-noise quantum processors connected through relatively noisy quantum links are capable of fault-tolerant operation as long as the noise can be confined to the interface. Finding protocols that implement the quantum links between modules as efficiently as possible is essential because inter-module entanglement is challenging to produce at a similar rate and fidelity as local entanglement. We introduce a protocol for lattice surgery on surface codes in which all non-local operations are Bell measurements. The protocol simultaneously confines the link noise and requires only half as many module-crossing gates as previously proposed protocols. To mitigate distance-reducing hook errors, we introduce a strategy of alternating the gate sequence between rounds of syndrome measurement, which prevents multiple hooks from simultaneously aligning with a logical operator in the code. We evaluate our protocol's performance when two logical qubits on separate modules are prepared in a logical Bell state. Circuit-level simulations under depolarizing noise show that the logical error suppression for a given entanglement rate between modules is consistently stronger compared to the best-performing alternative protocols for a wide range of link noise, with a typical 40% entanglement resource saving for a constant logical error rate. Our approach to protocol design is applicable to any quantum circuit that must be divided across processor modules and can therefore guide development of resource-efficient modular quantum computation beyond the surface code.
Distributed quantum computing can potentially address the scalability challenge by networking processors through photon-mediated remote entanglement. Prior approaches assumed that remote Bell pairs require distillation before use, incurring substantial overhead, to achieve sufficiently high fidelity. However, recent results show that lattice-surgery operations at logical qubit boundaries tolerate significantly higher error rates than previously assumed. We quantify the resource trade-offs between distillation overhead and surface-code distance requirements under realistic constraints including probabilistic entanglement generation and memory decoherence. We identify the fidelity crossover point separating the two regimes. Below this threshold, the distillation strategy dominates, reducing resource overhead by up to two orders of magnitude. Above it, no-distillation becomes the more efficient choice, reducing resource overhead by more than half. We briefly describe the application of these methods to ion-trap and neutral-atom platforms. These results provide joint design guidelines for optimizing photonic interconnects and fault-tolerant architectures in distributed quantum computing.
Modular quantum computing is a leading paradigm for scaling quantum computation beyond the resource limitations of monolithic devices. In this architecture, multiple quantum processing units (QPUs), employing identical or distinct qubit modalities, are interconnected via shared entanglement. Here, we investigate how errors at module interfaces and within individual QPUs affect fault-tolerant computation when qubits are encoded using the rotated surface code. Going beyond the logical-memory benchmark, we perform circuit-level simulations of fault-tolerant nonlocal CNOT gates implemented via lattice surgery between QPUs connected by noisy Bell pairs, and analyze the resulting logical error rates. Our results show that interfaces can tolerate noise up to an order of magnitude higher than intra-QPU noise, with only a minor reduction in the fault-tolerance threshold. We further develop an efficient protocol for preparing distributed fault-tolerant logical GHZ states, reducing ancilla overhead, time, and nonlocal Bell-pair consumption. We show that ancilla minimization in this setting is equivalent to a vertex-cover problem on an associated graph, and introduce a polynomial-time heuristic algorithm for finding low-overhead solutions. Our results provide quantitative evidence that distributed quantum error correction can enable scalable, fault-tolerant quantum computation in modular architectures.
Modular architectures offer a scalable path toward fault-tolerant quantum computing by interconnecting smaller quantum processing units provided that high-rate, fault-tolerant interfaces can be realized across modules. We present a comprehensive analysis and comparison of known methods for establishing such interfaces, including lattice surgery, transversal gates, and grow-and-distill protocols based on code growing and logical distillation. Using the surface code, we identify optimal interface strategies across a wide range of hardware parameters, such as gate fidelities, entangling rates, and memory resources, and estimate the requirements to achieve logical error rates of 10 − 6 and 10 − 12 . Our results establish when the interface becomes a bottleneck in the computation and provide guidance for experimental implementations with superconducting, atomic, and solid-state hardware.
Fault tolerant quantum computation over distributed quantum computing (DQC) platforms requires careful evaluation of resource requirements and noise thresholds. As quantum hardware advances toward modular and networked architectures, various fault tolerant DQC schemes have been proposed, which can be broadly categorized into three architectural types. Type 1 architectures consist of small quantum nodes connected via Greenberger-Horne-Zeilinger (GHZ) states, enabling nonlocal stabilizer measurements. Type 2 architectures distribute a large error correcting code block across multiple modules, with most stabilizer measurements remaining local, except for a small subset at patch boundaries that are performed using nonlocal CNOT gates. Type 3 architectures assign code blocks to distinct modules and can perform fault tolerant operations such as transversal gates, lattice surgery, and teleportation to implement logical operations between code blocks. Using the planar surface code and toric code as representative examples, we analyze how the resource requirements, particularly the number of Bell pairs and the average number of generation attempts, scale with increasing code distance across different architectural designs. This analysis provides valuable insights for identifying architectures well suited to fault tolerant distributed quantum computation under near term hardware and resource constraints.
Low-overhead quantum error-correction schemes are essential for enabling quantum computation on registers containing multiple logical qubits. For planar architectures with limited nearest-neighbor qubit connectivity, the surface code has emerged as the leading paradigm. Recent theoretical and experimental work has shown that a physical-qubit connectivity of degree three is sufficient to implement fault-tolerant quantum error correction. In this work, we study lattice surgery in the context of such trivalent architectures and introduce scalable circuit constructions to implement it. Compared with the four-valent measurement scheme, the trivalent lattice-surgery protocol reduces the required resources by O(d)\mathcal{O}(d)O(d) qubits out of a total qubit count of O(d2)\mathcal{O}(d^2)O(d2) and by O(d)\mathcal{O}(d)O(d) two-qubit gates out of a total two-qubit gate count of O(d3)\mathcal{O}(d^3)O(d3). We benchmark the logical fidelity of both lattice-surgery schemes in terms of experimentally realistic simulations targeting an implementation with a fluxonium qubit based architecture and find a potential improvement of up to ≈25%\approx25\%≈25% for distance-three. These results open a way for scalable planar trivalent qubit architectures to host a surface-code-based logical quantum processor.