Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

arXiv:2607.27204

Fault-Tolerant Logical Operations and Efficient State Preparation in Modular Quantum Architectures with Noisy Interfaces

S. Siddardha Chelluri, Riccardo Mengoni, Tom Darras, Julien Laurat, Eleni Diamanti, Ioannis Lavdas

quant-phSubmitted Jul 29, 2026• Announced Jul 30, 2026• 0 citations• Revised Oct 22, 2026 (v2)
v1 · Jul 29, 2026v2 · Oct 22, 2026
arXivHTMLPDF

Abstract

Modular quantum computing is a leading paradigm for scaling quantum computation beyond the resource limitations of monolithic devices. In this architecture, multiple quantum processing units (QPUs), employing identical or distinct qubit modalities, are interconnected via shared entanglement. Here, we investigate how errors at module interfaces and within individual QPUs affect fault-tolerant computation when qubits are encoded using the rotated surface code. Going beyond the logical-memory benchmark, we perform circuit-level simulations of fault-tolerant nonlocal CNOT gates implemented via lattice surgery between QPUs connected by noisy Bell pairs, and analyze the resulting logical error rates. Our results show that interfaces can tolerate noise up to an order of magnitude higher than intra-QPU noise, with only a minor reduction in the fault-tolerance threshold. We further develop an efficient protocol for preparing distributed fault-tolerant logical GHZ states, reducing ancilla overhead, time, and nonlocal Bell-pair consumption. We show that ancilla minimization in this setting is equivalent to a vertex-cover problem on an associated graph, and introduce a polynomial-time heuristic algorithm for finding low-overhead solutions. Our results provide quantitative evidence that distributed quantum error correction can enable scalable, fault-tolerant quantum computation in modular architectures.

Comments
10 pages, 6 figures

Related papers

Lattice surgery with Bell measurements: Modular fault-tolerant quantum computation at low entanglement cost

Trond Hjerpekjøn Haug, Timo Hillmann, Anton Frisk Kockum +1 more

Modular architectures are a promising approach to scaling quantum computers to fault tolerance. Small, low-noise quantum processors connected through relatively noisy quantum links are capable of fault-tolerant operation as long as the noise can be confined to the interface. Finding protocols that implement the quantum links between modules as efficiently as possible is essential because inter-module entanglement is challenging to produce at a similar rate and fidelity as local entanglement. We introduce a protocol for lattice surgery on surface codes in which all non-local operations are Bell measurements. The protocol simultaneously confines the link noise and requires only half as many module-crossing gates as previously proposed protocols. To mitigate distance-reducing hook errors, we introduce a strategy of alternating the gate sequence between rounds of syndrome measurement, which prevents multiple hooks from simultaneously aligning with a logical operator in the code. We evaluate our protocol's performance when two logical qubits on separate modules are prepared in a logical Bell state. Circuit-level simulations under depolarizing noise show that the logical error suppression for a given entanglement rate between modules is consistently stronger compared to the best-performing alternative protocols for a wide range of link noise, with a typical 40% entanglement resource saving for a constant logical error rate. Our approach to protocol design is applicable to any quantum circuit that must be divided across processor modules and can therefore guide development of resource-efficient modular quantum computation beyond the surface code.

arXiv:2510.13541•Oct 15, 2025•1 citation

Architectural Approaches to Fault-Tolerant Distributed Quantum Computing and Their Entanglement Overheads

Nitish Kumar Chandra, Eneet Kaur, Kaushik P. Seshadreesan

Fault tolerant quantum computation over distributed quantum computing (DQC) platforms requires careful evaluation of resource requirements and noise thresholds. As quantum hardware advances toward modular and networked architectures, various fault tolerant DQC schemes have been proposed, which can be broadly categorized into three architectural types. Type 1 architectures consist of small quantum nodes connected via Greenberger-Horne-Zeilinger (GHZ) states, enabling nonlocal stabilizer measurements. Type 2 architectures distribute a large error correcting code block across multiple modules, with most stabilizer measurements remaining local, except for a small subset at patch boundaries that are performed using nonlocal CNOT gates. Type 3 architectures assign code blocks to distinct modules and can perform fault tolerant operations such as transversal gates, lattice surgery, and teleportation to implement logical operations between code blocks. Using the planar surface code and toric code as representative examples, we analyze how the resource requirements, particularly the number of Bell pairs and the average number of generation attempts, scale with increasing code distance across different architectural designs. This analysis provides valuable insights for identifying architectures well suited to fault tolerant distributed quantum computation under near term hardware and resource constraints.

quant-pharXiv:2511.13657•IEEE International Conference on Trust, Privacy and Security in Intelligent Systems and Applications (TPS-ISA)•Nov 18, 2025•1 citation

Fault-tolerant interfaces for modular quantum computing on diverse qubit platforms

Frederik K. Marqversen, Gefen Baranes, Maxim A. Sirotin +1 more

Modular architectures offer a scalable path toward fault-tolerant quantum computing by interconnecting smaller quantum processing units provided that high-rate, fault-tolerant interfaces can be realized across modules. We present a comprehensive analysis and comparison of known methods for establishing such interfaces, including lattice surgery, transversal gates, and grow-and-distill protocols based on code growing and logical distillation. Using the surface code, we identify optimal interface strategies across a wide range of hardware parameters, such as gate fidelities, entangling rates, and memory resources, and estimate the requirements to achieve logical error rates of 10 − 6 and 10 − 12 . Our results establish when the interface becomes a bottleneck in the computation and provide guidance for experimental implementations with superconducting, atomic, and solid-state hardware.

arXiv:2510.05221•Physical Review Research•Mar 18, 2026•1 citation

Error Suppression in Distributed Quantum Computing with Heterogeneous-Distance Lattice Surgery

Daniel Dilley, Anastashia Jebraeilli, Rayat Roy +3 more

Distributed quantum computing requires fault-tolerant operations across inter-QPU links that can be substantially noisier than local gates. Uniformly increasing code distance provides additional protection but also enlarges data patches used for local storage and computation. Here, we introduce distributed heterogeneous-distance lattice surgery using an eight-data-patch ancilla-mediated (8-DAM) architecture, which will be useful for near-term quantum devices with less qubit overhead. In this architecture, the central ancilla spanning the inter-QPU boundary is enlarged while the data patches retain distance $d$. The protocol uses traveling stabilizers to suppress hook errors during merge and split operations between these unequal-distance patches. Circuit-level simulations of rotated surface codes at fixed local depolarizing noise show that logical-readout error rates depend only weakly on link noise. The resulting advantage over conventional lattice surgery grows as link errors increase. Comparisons with uniform distance implementations demonstrate comparable logical error suppression with reduced physical-qubit overhead. We also demonstrate how 8-DAM layouts support two simultaneous distributed logical CNOT operations between four logical data qubits using a single enlarged ancilla. At higher link noise, this construction yields lower logical error rates and more stability than two independent distributed logical CNOTs. These results support selective ancilla enlargement as a resource-efficient approach to fault-tolerant distributed quantum computing.

quant-pharXiv:2609.26784•Sep 23, 2026•0 citations

Distributed Quantum Error Correction with Bivariate Bicycle Codes in a Modular Architecture

Nitish Kumar Chandra, Eneet Kaur, Reza Nejabati +1 more

Quantum low density parity check (qLDPC) codes, particularly bivariate bicycle (BB) codes, achieve competitive fault tolerance thresholds while offering substantially higher encoding rates than planar surface codes. However, their intrinsically long-range stabilizer structure makes them difficult to implement on monolithic devices with nearest neighbor connectivity and limited qubit capacity. In this work, we study the realization of a BB code in a modular multiprocessor architecture, where quantum processors are interconnected through shared Bell pairs. We consider processors with all to all internal connectivity, which is feasible on trapped ion and neutral atom platforms, enabling flexible local gate execution while inter-processor (nonlocal) gates are mediated by shared entanglement. We describe a star network architecture that can realize this distributed setting. We partition the qubits of the [[144,12,12]] BB code across 4, 6, and 12 quantum processors and analyze the resulting logical error rates and pseudo-threshold performance under circuit level noise by varying the number of processors and a scaling factor that captures the additional noise associated with nonlocal operations. We use Monte Carlo simulations with BP+OSD decoding and extend the previously known BB code ansatz to the distributed setting. Our results provide architectural insight and design considerations for distributed BB codes in modular quantum computing architectures.

quant-pharXiv:2605.04663•May 7, 2026•0 citations

Resource-adaptive distributed fault tolerance with very noisy Bell pairs

Moritz Schmidt, Martin Moureau, Benjamin Rodatz +3 more

Distributed architectures have been proposed as a pathway to large-scale quantum computers. Combined with the need for fault-tolerance, such architectures require distributed quantum error correction (DQEC) and distributed logical gates. An important challenge is how to realize DQEC primitives in the setting where interaction between modules is restricted to shared Bell pairs that are significantly noisier than on-chip operations. We extend the framework known as fault tolerance by construction to this setting, deriving different strategies for handling the additional noise. Through fault-improvement we recover conventional entanglement distillation, and also find more dynamical protocols that enable space-time trade-offs. We show that integrated decoding halves the required distillation code distance compared to entanglement distillation implemented using separate decoding, thus requiring significantly fewer Bell pairs. As a main focus of the work, we synthesize efficient circuits for an important primitive in distributed fault tolerance: distributed stabilizer measurements. These circuits can be adapted to resource constraints, e.g. on the Bell pair generation rate or the space available for on-chip auxiliary qubits. Noting that full local fault-tolerance is not always needed to preserve the correct scaling of logical error rates, we further optimize the circuits depending on the surrounding context. We consider in particular the surface code and the color code, both as distributed memories and in the case of lattice surgery across separate modules. Here, robustness to certain hook and readout errors reduces the number of required Bell pairs even further, compared to the context-free setting. We numerically benchmark the resulting implementations under circuit level noise with additional interconnect noise.

quant-pharXiv:2609.03048•Sep 4, 2026•0 citations
Modular quantum computing is a leading paradigm for scaling quantum computation beyond the resource limitations of monolithic devices. In this architecture, multiple quantum processing units (QPUs), employing identical or distinct qubit modalities, are interconnected via shared entanglement. Here, we investigate how errors at module interfaces and within individual QPUs affect fault-tolerant computation when qubits are encoded using the rotated surface code. Going beyond the logical-memory benchmark, we perform circuit-level simulations of fault-tolerant nonlocal CNOT gates implemented via lattice surgery between QPUs connected by noisy Bell pairs, and analyze the resulting logical error rates. Our results show that interfaces can tolerate noise up to an order of magnitude higher than intra-QPU noise, with only a minor reduction in the fault-tolerance threshold. We further develop an efficient protocol for preparing distributed fault-tolerant logical GHZ states, reducing ancilla overhead, time, and nonlocal Bell-pair consumption. We show that ancilla minimization in this setting is equivalent to a vertex-cover problem on an associated graph, and introduce a polynomial-time heuristic algorithm for finding low-overhead solutions. Our results provide quantitative evidence that distributed quantum error correction can enable scalable, fault-tolerant quantum computation in modular architectures.
Modular architectures are a promising approach to scaling quantum computers to fault tolerance. Small, low-noise quantum processors connected through relatively noisy quantum links are capable of fault-tolerant operation as long as the noise can be confined to the interface. Finding protocols that implement the quantum links between modules as efficiently as possible is essential because inter-module entanglement is challenging to produce at a similar rate and fidelity as local entanglement. We introduce a protocol for lattice surgery on surface codes in which all non-local operations are Bell measurements. The protocol simultaneously confines the link noise and requires only half as many module-crossing gates as previously proposed protocols. To mitigate distance-reducing hook errors, we introduce a strategy of alternating the gate sequence between rounds of syndrome measurement, which prevents multiple hooks from simultaneously aligning with a logical operator in the code. We evaluate our protocol's performance when two logical qubits on separate modules are prepared in a logical Bell state. Circuit-level simulations under depolarizing noise show that the logical error suppression for a given entanglement rate between modules is consistently stronger compared to the best-performing alternative protocols for a wide range of link noise, with a typical 40% entanglement resource saving for a constant logical error rate. Our approach to protocol design is applicable to any quantum circuit that must be divided across processor modules and can therefore guide development of resource-efficient modular quantum computation beyond the surface code.
Fault tolerant quantum computation over distributed quantum computing (DQC) platforms requires careful evaluation of resource requirements and noise thresholds. As quantum hardware advances toward modular and networked architectures, various fault tolerant DQC schemes have been proposed, which can be broadly categorized into three architectural types. Type 1 architectures consist of small quantum nodes connected via Greenberger-Horne-Zeilinger (GHZ) states, enabling nonlocal stabilizer measurements. Type 2 architectures distribute a large error correcting code block across multiple modules, with most stabilizer measurements remaining local, except for a small subset at patch boundaries that are performed using nonlocal CNOT gates. Type 3 architectures assign code blocks to distinct modules and can perform fault tolerant operations such as transversal gates, lattice surgery, and teleportation to implement logical operations between code blocks. Using the planar surface code and toric code as representative examples, we analyze how the resource requirements, particularly the number of Bell pairs and the average number of generation attempts, scale with increasing code distance across different architectural designs. This analysis provides valuable insights for identifying architectures well suited to fault tolerant distributed quantum computation under near term hardware and resource constraints.
Modular architectures offer a scalable path toward fault-tolerant quantum computing by interconnecting smaller quantum processing units provided that high-rate, fault-tolerant interfaces can be realized across modules. We present a comprehensive analysis and comparison of known methods for establishing such interfaces, including lattice surgery, transversal gates, and grow-and-distill protocols based on code growing and logical distillation. Using the surface code, we identify optimal interface strategies across a wide range of hardware parameters, such as gate fidelities, entangling rates, and memory resources, and estimate the requirements to achieve logical error rates of 10 − 6 and 10 − 12 . Our results establish when the interface becomes a bottleneck in the computation and provide guidance for experimental implementations with superconducting, atomic, and solid-state hardware.
Distributed quantum computing requires fault-tolerant operations across inter-QPU links that can be substantially noisier than local gates. Uniformly increasing code distance provides additional protection but also enlarges data patches used for local storage and computation. Here, we introduce distributed heterogeneous-distance lattice surgery using an eight-data-patch ancilla-mediated (8-DAM) architecture, which will be useful for near-term quantum devices with less qubit overhead. In this architecture, the central ancilla spanning the inter-QPU boundary is enlarged while the data patches retain distance ddd. The protocol uses traveling stabilizers to suppress hook errors during merge and split operations between these unequal-distance patches. Circuit-level simulations of rotated surface codes at fixed local depolarizing noise show that logical-readout error rates depend only weakly on link noise. The resulting advantage over conventional lattice surgery grows as link errors increase. Comparisons with uniform distance implementations demonstrate comparable logical error suppression with reduced physical-qubit overhead. We also demonstrate how 8-DAM layouts support two simultaneous distributed logical CNOT operations between four logical data qubits using a single enlarged ancilla. At higher link noise, this construction yields lower logical error rates and more stability than two independent distributed logical CNOTs. These results support selective ancilla enlargement as a resource-efficient approach to fault-tolerant distributed quantum computing.
Quantum low density parity check (qLDPC) codes, particularly bivariate bicycle (BB) codes, achieve competitive fault tolerance thresholds while offering substantially higher encoding rates than planar surface codes. However, their intrinsically long-range stabilizer structure makes them difficult to implement on monolithic devices with nearest neighbor connectivity and limited qubit capacity. In this work, we study the realization of a BB code in a modular multiprocessor architecture, where quantum processors are interconnected through shared Bell pairs. We consider processors with all to all internal connectivity, which is feasible on trapped ion and neutral atom platforms, enabling flexible local gate execution while inter-processor (nonlocal) gates are mediated by shared entanglement. We describe a star network architecture that can realize this distributed setting. We partition the qubits of the [[144,12,12]] BB code across 4, 6, and 12 quantum processors and analyze the resulting logical error rates and pseudo-threshold performance under circuit level noise by varying the number of processors and a scaling factor that captures the additional noise associated with nonlocal operations. We use Monte Carlo simulations with BP+OSD decoding and extend the previously known BB code ansatz to the distributed setting. Our results provide architectural insight and design considerations for distributed BB codes in modular quantum computing architectures.
Distributed architectures have been proposed as a pathway to large-scale quantum computers. Combined with the need for fault-tolerance, such architectures require distributed quantum error correction (DQEC) and distributed logical gates. An important challenge is how to realize DQEC primitives in the setting where interaction between modules is restricted to shared Bell pairs that are significantly noisier than on-chip operations. We extend the framework known as fault tolerance by construction to this setting, deriving different strategies for handling the additional noise. Through fault-improvement we recover conventional entanglement distillation, and also find more dynamical protocols that enable space-time trade-offs. We show that integrated decoding halves the required distillation code distance compared to entanglement distillation implemented using separate decoding, thus requiring significantly fewer Bell pairs. As a main focus of the work, we synthesize efficient circuits for an important primitive in distributed fault tolerance: distributed stabilizer measurements. These circuits can be adapted to resource constraints, e.g. on the Bell pair generation rate or the space available for on-chip auxiliary qubits. Noting that full local fault-tolerance is not always needed to preserve the correct scaling of logical error rates, we further optimize the circuits depending on the surrounding context. We consider in particular the surface code and the color code, both as distributed memories and in the case of lattice surgery across separate modules. Here, robustness to certain hook and readout errors reduces the number of required Bell pairs even further, compared to the context-free setting. We numerically benchmark the resulting implementations under circuit level noise with additional interconnect noise.