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arXiv:2607.15044

Towards logical entanglement creation in trivalent planar architectures

Lukas Bödeker, Luis Colmenarez, Sergey Blinov, Ants Remm, Simon Gustavsson, Markus Müller

quant-phSubmitted Jul 16, 2026• Announced Jul 17, 2026• 0 citations• Revised Jul 22, 2026 (v2)
v1 · Jul 16, 2026v2 · Jul 22, 2026
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Abstract

Low-overhead quantum error-correction schemes are essential for enabling quantum computation on registers containing multiple logical qubits. For planar architectures with limited nearest-neighbor qubit connectivity, the surface code has emerged as the leading paradigm. Recent theoretical and experimental work has shown that a physical-qubit connectivity of degree three is sufficient to implement fault-tolerant quantum error correction. In this work, we study lattice surgery in the context of such trivalent architectures and introduce scalable circuit constructions to implement it. Compared with the four-valent measurement scheme, the trivalent lattice-surgery protocol reduces the required resources by $\mathcal{O}(d)$ qubits out of a total qubit count of $\mathcal{O}(d^2)$ and by $\mathcal{O}(d)$ two-qubit gates out of a total two-qubit gate count of $\mathcal{O}(d^3)$. We benchmark the logical fidelity of both lattice-surgery schemes in terms of experimentally realistic simulations targeting an implementation with a fluxonium qubit based architecture and find a potential improvement of up to $\approx25\%$ for distance-three. These results open a way for scalable planar trivalent qubit architectures to host a surface-code-based logical quantum processor.

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Low-overhead quantum error-correction schemes are essential for enabling quantum computation on registers containing multiple logical qubits. For planar architectures with limited nearest-neighbor qubit connectivity, the surface code has emerged as the leading paradigm. Recent theoretical and experimental work has shown that a physical-qubit connectivity of degree three is sufficient to implement fault-tolerant quantum error correction. In this work, we study lattice surgery in the context of such trivalent architectures and introduce scalable circuit constructions to implement it. Compared with the four-valent measurement scheme, the trivalent lattice-surgery protocol reduces the required resources by O(d)\mathcal{O}(d)O(d) qubits out of a total qubit count of O(d2)\mathcal{O}(d^2)O(d2) and by O(d)\mathcal{O}(d)O(d) two-qubit gates out of a total two-qubit gate count of O(d3)\mathcal{O}(d^3)O(d3). We benchmark the logical fidelity of both lattice-surgery schemes in terms of experimentally realistic simulations targeting an implementation with a fluxonium qubit based architecture and find a potential improvement of up to ≈25%\approx25\%≈25% for distance-three. These results open a way for scalable planar trivalent qubit architectures to host a surface-code-based logical quantum processor.
Fault-tolerant logical operations are fundamental for scalable quantum computation. Here, we report the experimental realization of lattice-surgery operations between a pair of distance-three surface-code logical qubits on a planar superconducting processor. During repeated syndrome extraction cycles, the logical qubits exhibit per-cycle error rates of 0.0365(2)0.0365(2)0.0365(2) and 0.0282(1)0.0282(1)0.0282(1), respectively, after leakage events are rejected. By leveraging joint initialization and lattice splitting, we deterministically prepare a logical Bell state, confirming genuine bipartite entanglement via the error-corrected logical state fidelity. We further execute a two-qubit Deutsch-Jozsa algorithm at the logical level to demonstrate algorithmic utility in a fault-tolerant framework. Finally, to achieve universal control, we implement magic-state injection and gate teleportation to realize continuous non-Clifford rotations about the logical XXX axis. For the logical RX(π/4)R_{X}(π/4)RX​(π/4) gate, we achieve a logical gate fidelity of 0.943−9+100.943_{-9}^{+10}0.943−9+10​ conditioned on the absence of detected errors. These results establish lattice surgery as a practical and versatile paradigm for logical computation in near-term surface-code architectures, representing a critical milestone toward scalable fault-tolerant quantum advantage in superconducting circuits.
Quantum error correction is needed for quantum computers to be capable of executing algorithms using hundreds of logical qubits in a fault-tolerant manner. Recent experiments have progressed towards this by demonstrating sufficiently low error rates for state preservation of a single logical qubit. However, quantum computation algorithms also require that these logical qubits can be entangled and that gate operations can be performed on them. Lattice surgery is a technique that offers a practical approach for implementing such gates, particularly in planar quantum processor layouts. Here we demonstrate lattice surgery between two distance-three repetition-code qubits by splitting a single distance-three surface-code qubit. Using a quantum circuit that is fault-tolerant for bit-flip errors, we achieve an improvement in the value of the decoded ZZ logical two-qubit observable compared with a similar non-encoded circuit. We therefore demonstrate the functional building blocks needed for lattice-surgery operations on larger-distance codes based on superconducting circuits.
In the era of early fault-tolerant quantum computing, basic demonstrations of entanglement operations between a few logical qubits are at the frontier of recent developments in quantum computing. In this work, we describe in detail, at both the logical and physical qubit levels, a logical teleportation protocol between two surface code logical qubits based on lattice surgery. We address several aspects of the teleportation protocol pertinent to superconducting qubit architectures. We explore the modularity constraints in the number and location of stabilizer readouts and compare variants of the teleportation protocol in this regard. Additionally, we investigate potential performance improvements related to in-sequence decision logic and the optimal size of the interface region between two surface code patches on a superconducting chip. Based on our simulations, we show possible near-term improvements in lattice surgery protocols that facilitate fault-tolerant quantum computing in superconducting circuit architectures.
Abstract Quantum error correction is needed for quantum computers to be capable of executing algorithms using hundreds of logical qubits in a fault-tolerant manner. Recent experiments have progressed towards this by demonstrating sufficiently low error rates for state preservation of a single logical qubit. However, quantum computation algorithms also require that these logical qubits can be entangled and that gate operations can be performed on them. Lattice surgery is a technique that offers a practical approach for implementing such gates, particularly in planar quantum processor layouts. Here we demonstrate lattice surgery between two distance-three repetition-code qubits by splitting a single distance-three surface-code qubit. Using a quantum circuit that is fault-tolerant for bit-flip errors, we achieve an improvement in the value of the decoded Z Z logical two-qubit observable compared with a similar non-encoded circuit. We therefore demonstrate the functional building blocks needed for lattice-surgery operations on larger-distance codes based on superconducting circuits.
Efforts are being made to develop quantum processors beyond planar connectivity and quantum error correction codes suitable for 3-dimensional structures. In this study, we propose 3-dimensional architectures of logical data qubits and logical ancilla qubits based on surface codes using lattice surgery in situations where 3-dimensional nearest-neighbor connectivity between physical qubits is guaranteed. We also propose a method for performing CNOT operations on the proposed architecture. We present a physical qubit structure that stacks 2-dimensional physical qubit layers and adds several additional physical qubits for lattice surgery between adjacent layers. Our design permits the fast transversal application of CNOT operations between logical qubits in a nearest-neighbor relationship on adjacent layers, which is three times faster than the speed of standard lattice surgery CNOTs. Our design also permits the performance of CNOT operations between logical qubits that are far from each other using fast SWAP operations with transversal CNOT and lattice surgery. To demonstrate the advantages of our architecture, we present the required number of qubits and time for benchmark circuits on the proposed architecture and compare the required qubits and time on the checkerboard architecture and row-type architecture which are a 2-dimensional architectures to show the advantages of our architecture.
In order to achieve error rates necessary for advantageous quantum algorithms, Quantum Error Correction (QEC) will need to be employed, improving logical qubit fidelity beyond what can be achieved physically. As today's devices begin to scale, co-designing architectures for QEC with the underlying hardware will be necessary to reduce the daunting overheads and accelerate the realization of practical quantum computing. In this work, we focus on logical computation in QEC. We address quantum computers made from neutral atom arrays to design a surface code architecture that translates the hardware's higher physical connectivity into a higher logical connectivity. We propose groups of interleaved logical qubits, gaining all-to-all connectivity within the group via efficient transversal CNOT gates. Compared to standard lattice surgery operations, this reduces both the overall qubit footprint and execution time, lowering the spacetime overhead needed for small-scale QEC circuits. We also explore the architecture's scalability. We look at using physical atom movement schemes and propose interleaved lattice surgery which allows an all-to-all connectivity between qubits in adjacent interleaved groups, creating a higher connectivity routing space for large-scale circuits. Using numerical simulations, we evaluate the total routing time of interleaved lattice surgery and atom movement for various circuit sizes. We identify a cross-over point defining intermediate-scale circuits where atom movement is best and large-scale circuits where interleaved lattice surgery is best. We use this to motivate a hybrid approach as devices continue to scale, with the choice of operation depending on the routing distance.