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Software/Hardware Co-Design of Fault-Tolerant Quantum Systems

Joshua Viszlai

Published Jun 1, 2026• 0 citations
Publisher

Abstract

Quantum computing is positioned to be a transformative technology to key areas of scientific interest such as quantum chemistry, material science, and cryptography. At a hardware level, recent years have seen broad progress in a variety of qubit modalities, however, error rates are still orders of magnitude higher than what is necessary for large-scale quantum programs. This gap in error rates motivates the use of quantum error correction (QEC) and the realization of fault-tolerant quantum computing (FTQC), yet today, although the theory of FTQC is promising, effectively connecting it to real devices poses significant challenges. In this dissertation we study opportunities for more efficient and scalable FTQC architectures through the co-design of quantum hardware and software. We first look at how unique hardware capabilities in quantum computers made from 2D arrays of optically trapped atoms can improve QEC performance. For computation, we study how longer-range interactions between atoms can enable a novel embedding of QEC blocks on physical qubits that improves logical-level connectivity. For memory, we study how mid-circuit movement of atoms can effectively implement higher encoding rate QEC codes, creating a qubit-efficient memory system. We next consider the performance impact of real-time classical systems in FTQC architectures, and explore the use of speculation to improve large-scale decoding systems. Finally, we study how software systems can be used to improve QEC designs. We consider the problem of QEC circuit optimization, and study an automated approach based on iterative optimization of performance-reducing subcircuits.

DOI
10.6082/q0hxa-tew90

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Quantum computing is positioned to be a transformative technology to key areas of scientific interest such as quantum chemistry, material science, and cryptography. At a hardware level, recent years have seen broad progress in a variety of qubit modalities, however, error rates are still orders of magnitude higher than what is necessary for large-scale quantum programs. This gap in error rates motivates the use of quantum error correction (QEC) and the realization of fault-tolerant quantum computing (FTQC), yet today, although the theory of FTQC is promising, effectively connecting it to real devices poses significant challenges. In this dissertation we study opportunities for more efficient and scalable FTQC architectures through the co-design of quantum hardware and software. We first look at how unique hardware capabilities in quantum computers made from 2D arrays of optically trapped atoms can improve QEC performance. For computation, we study how longer-range interactions between atoms can enable a novel embedding of QEC blocks on physical qubits that improves logical-level connectivity. For memory, we study how mid-circuit movement of atoms can effectively implement higher encoding rate QEC codes, creating a qubit-efficient memory system. We next consider the performance impact of real-time classical systems in FTQC architectures, and explore the use of speculation to improve large-scale decoding systems. Finally, we study how software systems can be used to improve QEC designs. We consider the problem of QEC circuit optimization, and study an automated approach based on iterative optimization of performance-reducing subcircuits.
Scalable quantum computation is expected to rely on fault-tolerant quantum computation (FTQC), in which quantum error correction (QEC) suppresses physical errors sufficiently to support reliable logical operations. This requires quantum compilation to move beyond general-purpose circuit optimization toward encoding-aware and protocol-structured compilation across the full stack of fault-tolerant quantum computers. Beyond circuit synthesis and hardware mapping, an FTQC compiler must lower algorithm-level operations into the logical gate set supported by the chosen code, coordinate encoded data and ancilla resources, realize logical operations together with repeated syndrome extraction under hardware constraints, and provide the resulting measurement stream to real-time decoding. This survey presents a full-stack view of compiler design for QEC-protected quantum computation. We organize existing work into three interacting layers: logical-level QEC compilation, physical-level QEC realization, and decoder runtime integration. At the logical level, we review surface-code lattice-surgery compilers, beyond-surface-code code-surgery frameworks including emerging qLDPC approaches, and compilation support for non-Clifford operations such as magic-state distillation and code switching. At the physical level, we survey hardware-aware QEC realization on superconducting, trapped-ion, and neutral-atom platforms. We further examine decoder models, real-time decoding systems, and frame-management mechanisms that close the feedback loop during fault-tolerant execution. Finally, we identify open challenges in cross-layer optimization, qLDPC compilation, compiler-decoder co-design, runtime adaptivity, and the development of integrated and benchmarkable FTQC compilation stacks. An actively maintained paper list is available at: github.com/chenghongz/QEC-compiler-design.
The transition from noisy intermediate-scale quantum (NISQ) processors to large-scale fault-tolerant machines requires more than incremental improvements in physical qubit fidelity. While advances in quantum error correction (QEC) theory continue to lower the theoretical overhead of quantum computing, much of this research remains abstracted from the physical realities of qubit implementations. This disconnect often results in hardware-agnostic designs that are inefficient or impractical to build. In this dissertation, I identify three primary gaps between theoretical QEC research and practical hardware: (1) the high levels of noise and temporal instability in experimental devices that impede scalable QEC; (2) the prohibitively large qubit and time costs of useful algorithms, driven largely by the limitations of the standard surface code; and (3) the failure of current resource estimates to account for hardware-level constraints, such as limited connectivity and the complexity of implementing non-local operations. To bridge these gaps, I propose a holistic, cross-stack approach where the error correction protocols and the physical hardware are designed in concert. By developing realistic device models and hardware-aware solutions at the lowest levels of the software stack, we can accelerate the path toward functional fault-tolerance. I present my work across three research thrusts: first, leveraging codesign to mitigate hardware-specific noise and reduce physical error rates; second, developing software tools for fault-tolerant quantum computers to reduce the space-time overhead of the QEC layer; and third, proposing two novel hardware-aware QEC architectures that provide practical, high-performance routes to scalable quantum computation.
Quantum error correction (QEC) represents the cornerstone technology for realizing fault-tolerant quantum computing, addressing the fundamental challenge of quantum state decoherence in noisy intermediate-scale quantum (NISQ) devices. This comprehensive review examines recent advances in QEC implementations from 2020-2024, spanning theoretical foundations to practical hardware demonstrations. We analyze the evolution from pioneering stabilizer codes to modern topological approaches, with particular emphasis on surface codes and low-density parity-check (LDPC) codes that have demonstrated below-threshold error correction in superconducting and trapped-ion systems. The paper provides a comparative analysis of classical and machine learning-based decoder algorithms, evaluating their performance through complexity analysis and threshold comparisons in real-time error correction scenarios. Through examination of breakthrough experiments by Google, IBM, Quantinuum, and emerging platforms, we assess the current state of fault-tolerant quantum computing and identify critical engineering challenges including correlated noise models, cryogenic control systems, and scalable logical gate implementations. Our quantitative analysis reveals that while significant progress has been made toward practical fault-tolerance thresholds, achieving the resource efficiency and reliability required for large-scale quantum computation remains challenging. We provide detailed resource estimates for key applications including Shor's algorithm and optimization problems, along with analysis of industry roadmaps toward thousand-logical-qubit systems. This review serves as a comprehensive guide for researchers and engineers working toward the next generation of fault-tolerant quantum computers, with particular focus on information-theoretic perspectives relevant to quantum information entropy and syndrome processing.
Quantum error correction (QEC) represents the cornerstone technology for realizing fault-tolerant quantum computing, addressing the fundamental challenge of quantum state decoherence in noisy intermediate-scale quantum (NISQ) devices. This comprehensive review examines recent advances in QEC implementations from 2020-2024, spanning theoretical foundations to practical hardware demonstrations. We analyze the evolution from pioneering stabilizer codes to modern topological approaches, with particular emphasis on surface codes and low-density parity-check (LDPC) codes that have demonstrated below-threshold error correction in superconducting and trapped-ion systems. The paper provides a comparative analysis of classical and machine learning-based decoder algorithms, evaluating their performance through complexity analysis and threshold comparisons in real-time error correction scenarios. Through examination of breakthrough experiments by Google, IBM, Quantinuum, and emerging platforms, we assess the current state of fault-tolerant quantum computing and identify critical engineering challenges including correlated noise models, cryogenic control systems, and scalable logical gate implementations. Our quantitative analysis reveals that while significant progress has been made toward practical fault-tolerance thresholds, achieving the resource efficiency and reliability required for large-scale quantum computation remains challenging. We provide detailed resource estimates for key applications including Shor's algorithm and optimization problems, along with analysis of industry roadmaps toward thousand-logical-qubit systems. This review serves as a comprehensive guide for researchers and engineers working toward the next generation of fault-tolerant quantum computers, with particular focus on information-theoretic perspectives relevant to quantum information entropy and syndrome processing.
Quantum computers have the potential to solve certain problems exponentially faster than classical computers. However, realizing this potential in practice is a major challenge, as it requires precise control over large-scale quantum systems operating at extremely low error rates. Quantum error correction (QEC) provides a path to achieving such error rates, but its substantial resource overhead poses a significant practical barrier. In addition, identifying which computational problems offer a provable quantum advantage—and which remain fundamentally intractable—remains an open question. This thesis presents progress towards addressing both of these challenges. The first part of this thesis describes advances that substantially reduce the resource overhead of QEC. We begin by presenting realizations of logical circuits in dynamically reconfigurable arrays of neutral atoms. By jointly decoding the logical qubits, we reduce the cost of implementing such transversal Clifford circuits by a factor proportional to the code distance. We then develop new theories of fault tolerance to extend these savings to universal quantum computation with magic state inputs. Finally, we introduce techniques for fast correlated decoding, enabling practical implementations of these improvements in experimental hardware. Collectively, these advances accelerate progress toward large-scale computation and reduce the cost of QEC by over an order of magnitude. The second part of the thesis explores the relative power of quantum and classical computation in combinatorial optimization, a class of problems that is ubiquitous in science and engineering and foundational to the theory of computational complexity. We experimentally implement the optimized quantum adiabatic algorithm (QAA) in neutral atom arrays and observe evidence of a superlinear speedup over classical simulated annealing on certain hard problem instances. To interpret these results, we develop a theoretical framework to compare the performance of QAA with a broad class of classical Markov chain Monte Carlo algorithms. We identify conditions under which a quantum quadratic speedup is achievable and propose modifications to the QAA to reliably realize this advantage. Together, these contributions advance both the practical implementation and theoretical understanding of quantum algorithms.
Quantum error correction (QEC) has transitioned from a theoretical promise to an experimental reality, with recent demonstrations of below-threshold logical qubits marking a turning point in the quest for fault-tolerant quantum computing. Over the past five years, breakthroughs in surface code implementations, low-latency decoders, and improved physical qubit fidelities have brought us to the brink of scalable logical qubit systems. Yet the road to practical quantum advantage remains steep: correlated noise, cryogenic control complexity, and the resource overhead of magic state distillation still pose major barriers. Here, we synthesize recent progress across superconductng, trapped-ion, and neutral-atom platforms, assess the state-of the-art in topological and LDPC codes, and highlight engineering challenges that must be overcome to achieve systems with thousands of logical qubits. We argue that the 2025-2035 decade will be decisive for quantum computing, with success hinging on co-design of hardware, software, and algorithms. This perspective outlines a roadmap for the next generation of fault tolerant systems and discusses the societal and economic implications of entering the era of practical quantum advantage.