Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

The architecture at the end of the quantum tunnel

Tzvetan S. Metodi

Published Jan 1, 2007• 0 citations
OpenAlex

Abstract

Quantum computing is an emerging field that offers revolutionary and exciting new ways to process, store, and transport information. Moreover, realizing large-scale quantum systems requires advances in science and engineering that are now very close to reality. Such systems will need many classical and quantum parts that must fit together into one architecture, in which each component plays an integral role over the course of an application execution. Therefore, it is important that we draw upon the experiences gained from traditional architectures, to develop a model for a large-scale quantum system that provides the methodology necessary for the many different components to work together. In this thesis, I describe the design of the Quantum Logic Array (QLA) architecture, which tackles critical scalability issues such as the cost of error correction and distributing data over large-distances. To accurately model the performance of the QLA architecture—the ion-trap technology is used since every component necessary for universal quantum computation has been demonstrated in the laboratory. However, due to its design approach for maximizing parallelism, the QLA system suffers from large area overhead. To combat the area problem, I describe an architecture that uses the concept of hardware specialization employed in traditional architectures. The new architecture is based on the QLA model, but is divided into separately optimized quantum memory hierarchy and logic specific regions. The result is a scalable system design that exploits the available parallelism to balance both quantum and classical resources, while both reducing the area of the chip and increasing its performance.

Related papers

A Quantum Logic Array Microarchitecture: Scalable Quantum Data Movement and Computation

Tzvetan S. Metodi, Darshan Thaker, Andrew W. Cross

Recent experimental advances have demonstrated technologies capable of supporting scalable quantum computation. A critical next step is how to put those technologies together into a scalable, fault-tolerant system that is also feasible. We propose a quantum logic array (QLA) microarchitecture that forms the foundation of such a system. The QLA focuses on the communication resources necessary to efficiently support fault-tolerant computations. We leverage the extensive groundwork in quantum error correction theory and provide analysis that shows that our system is both asymptotically and empirically fault tolerant. Specifically, we use the QLA to implement a hierarchical, array-based design and a logarithmic expense quantum-teleportation communication protocol. Our goal is to overcome the primary scalability challenges of reliability, communication, and quantum resource distribution that plague current proposals for large-scale quantum computing. Our work complements recent work by Balenseifer et al. (2005), which studies the software tool chain necessary to simplify development of quantum applications; here we focus on modeling a full-scale optimized microarchitecture for scalable computing.

arXiv:quant-ph/0509051•IEEE/ACM International Symposium on Microarchitecture (MICRO)•Oct 11, 2006•109 citations

Quantum Memory Hierarchies: Efficient Designs to Match Available Parallelism in Quantum Computing

Darshan Thaker, Tzvetan S. Metodi, Andrew W. Cross +2 more

The assumption of maximum parallelism support for the successful realization of scalable quantum computers has led to homogeneous, "sea-of-qubits" architectures. The resulting architectures overcome the primary challenges of reliability and scalability at the cost of physically unacceptable system area. We find that by exploiting the natural serialization at both the application and the physical microarchitecture level of a quantum computer, we can reduce the area requirement while improving performance. In particular we present a scalable quantum architecture design that employs specialization of the system into memory and computational regions, each individually optimized to match hardware support to the available parallelism. Through careful application and system analysis, we find that our new architecture can yield up to a factor of thirteen savings in area due to specialization. In addition, by providing a memory hierarchy design for quantum computers, we can increase time performance by a factor of eight. This result brings us closer to the realization of a quantum processor that can solve meaningful problems

arXiv:quant-ph/0604070•Proceedings - International Symposium on Computer Architecture/Proceedings•Jul 21, 2006•43 citations

High-level interconnect model for the quantum logic array architecture

Tzvetan S. Metodi, Darshan Thaker, Andrew W. Cross +2 more

We summarize the main characteristics of the quantum logic array (QLA) architecture with a careful look at the key issues not described in the original conference publications: primarily, the teleportation-based logical interconnect. The design goal of the the quantum logic array architecture is to illustrate a model for a large-scale quantum architecture that solves the primary challenges of system-level reliability and data distribution over large distances. The QLA's logical interconnect design, which employs the quantum repeater protocol, is in principle capable of supporting the communication requirements for applications as large as the factoring of a 2048-bit number using Shor's quantum factoring algorithm. Our physical-level assumptions and architectural component validations are based on the trapped ion technology for implementing quantum computing.

ACM Journal on Emerging Technologies in Computing Systems•Mar 1, 2008•13 citations

Quantum Memory Hierarchies

Darshan Thaker, Tzvetan S. Metodi, Andrew W. Cross +2 more

The assumption of maximum parallelism support for the successful realization of scalable quantum computers has led to homogeneous, "sea-of-qubits" architectures. The resulting architectures overcome the primary challenges of reliability and scalability at the cost of physically unacceptable system area. We find that by exploiting the natural serialization at both the application and the physical microarchitecture level of a quantum computer, we can reduce the area requirement while improving performance. In particular we present a scalable quantum architecture design that employs specialization of the system into memory and computational regions, each individually optimized to match hardware support to the available parallelism. Through careful application and system analysis, we find that our new architecture can yield up to a factor of thirteen savings in area due to specialization. In addition, by providing a memory hierarchy design for quantum computers, we can increase time performance by a factor of eight. This result brings us closer to the realization of a quantum processor that can solve meaningful problems.

ACM SIGARCH Computer Architecture News•May 1, 2006•52 citations

Architecting efficiency, performance, and scalability for quantum computers

Margaret Martonosi, Eric C. Chi

This thesis addresses the design of a quantum computer (QC) architecture. Quantum error correction is a dominant factor as it is required to protect quantum bits (qubits) from decoherence. However, error correction's costs are substantial and call for a scale-up of 100X more qubits and instruction-level parallelism (ILP) on the order of 10,000 simultaneous operations per cycle. These are daunting challenges for a QC architect, who must balance demands in performance, control efficiency, and scalability of design. Error modeling is important for designing a QC so that error correction implementations and microarchitecture designs may be evaluated for effectiveness. This thesis presents a new deterministic approach to error modeling that is on the order of 1000X faster than previous Monte Carlo error models. While the deterministic error model is memory limited, it is capable of evaluating useful problems containing on the order of a dozen logical qubits encoded in the [[7,1,3]] quantum error correcting code (QECC). This dissertation presents a new QC processor architecture that leverages highly mobile qubits found in some QC technologies such as electron-spins on liquid helium (eSHe). The processor architecture presented here is designed to efficiently handle at least an order of magnitude more ILP than previously proposed designs, and it accommodates increasing ILP with size and latency costs scaling only linearly. Compilers are also crucial to a computer's performance and efficiency, and this dissertation describes new compiler optimizations including one that reduces hardware requirements by 25% with no performance loss. Multiple QC processors may be organized into a tiled configuration to provide sufficient ILP across the entire QC. This dissertation proposes a new distributed block tiling strategy that distributes encoded block qubits across arrays of data tiles and offloads non-critical path error correction routines to separate ancilla tiles. This strategy reduces tile capacity requirements by over 100X with the [[21,3,5]] QECC and achieves a simulated speedup of 2.8X for the eSHe QC when compared to the traditional tiling approach. In summary, this dissertation presents a novel QC architecture and design tools that improve performance and scalability while making efficient use of both control and qubit resources.

•Jan 1, 2009•0 citations

A Quantum von Neumann Architecture for Large-Scale Quantum Computing

Matthias F. Brandl

As the size of quantum systems becomes bigger, more complicated hardware is required to control these systems. In order to reduce the complexity, I discuss the amount of parallelism required for a fault-tolerant quantum computer and what computation speed can be achieved in different architectures. To build a large-scale quantum computer, one can use architectural principles, from classical computer architecture, like multiplexing or pipelining. In this document, a Quantum von Neumann architecture is introduced which uses specialized hardware for the different tasks of a quantum computer, like computation or storage. Furthermore, it requires long qubit coherence and the capability to move quantum information between the different parts of the quantum computer. As an example, a Quantum von Neumann architecture for trapped ions is presented which incorporates multiplexing in the memory region for large-scale quantum computation. To illustrate the capability of this architecture, a model trapped ion quantum computer based on Quantum von Neumann architecture, the Quantum 4004, is introduced. Its hardware is optimized for simplicity and uses the classical Intel 4004 CPU from 1971 as a blueprint. The Quantum 4004 has only a single processing zone and is structured in 4 qubit packages. Its quantum memory can store up to 32768 qubit ions and its computation speed is 10 $μ$s for single qubit operations and 20 $μ$s for two-qubit operations.

arXiv:1702.02583•Feb 8, 2017•24 citations
Quantum computing is an emerging field that offers revolutionary and exciting new ways to process, store, and transport information. Moreover, realizing large-scale quantum systems requires advances in science and engineering that are now very close to reality. Such systems will need many classical and quantum parts that must fit together into one architecture, in which each component plays an integral role over the course of an application execution. Therefore, it is important that we draw upon the experiences gained from traditional architectures, to develop a model for a large-scale quantum system that provides the methodology necessary for the many different components to work together.
In this thesis, I describe the design of the Quantum Logic Array (QLA) architecture, which tackles critical scalability issues such as the cost of error correction and distributing data over large-distances. To accurately model the performance of the QLA architecture—the ion-trap technology is used since every component necessary for universal quantum computation has been demonstrated in the laboratory. However, due to its design approach for maximizing parallelism, the QLA system suffers from large area overhead. To combat the area problem, I describe an architecture that uses the concept of hardware specialization employed in traditional architectures. The new architecture is based on the QLA model, but is divided into separately optimized quantum memory hierarchy and logic specific regions. The result is a scalable system design that exploits the available parallelism to balance both quantum and classical resources, while both reducing the area of the chip and increasing its performance.
Recent experimental advances have demonstrated technologies capable of supporting scalable quantum computation. A critical next step is how to put those technologies together into a scalable, fault-tolerant system that is also feasible. We propose a quantum logic array (QLA) microarchitecture that forms the foundation of such a system. The QLA focuses on the communication resources necessary to efficiently support fault-tolerant computations. We leverage the extensive groundwork in quantum error correction theory and provide analysis that shows that our system is both asymptotically and empirically fault tolerant. Specifically, we use the QLA to implement a hierarchical, array-based design and a logarithmic expense quantum-teleportation communication protocol. Our goal is to overcome the primary scalability challenges of reliability, communication, and quantum resource distribution that plague current proposals for large-scale quantum computing. Our work complements recent work by Balenseifer et al. (2005), which studies the software tool chain necessary to simplify development of quantum applications; here we focus on modeling a full-scale optimized microarchitecture for scalable computing.
The assumption of maximum parallelism support for the successful realization of scalable quantum computers has led to homogeneous, "sea-of-qubits" architectures. The resulting architectures overcome the primary challenges of reliability and scalability at the cost of physically unacceptable system area. We find that by exploiting the natural serialization at both the application and the physical microarchitecture level of a quantum computer, we can reduce the area requirement while improving performance. In particular we present a scalable quantum architecture design that employs specialization of the system into memory and computational regions, each individually optimized to match hardware support to the available parallelism. Through careful application and system analysis, we find that our new architecture can yield up to a factor of thirteen savings in area due to specialization. In addition, by providing a memory hierarchy design for quantum computers, we can increase time performance by a factor of eight. This result brings us closer to the realization of a quantum processor that can solve meaningful problems
We summarize the main characteristics of the quantum logic array (QLA) architecture with a careful look at the key issues not described in the original conference publications: primarily, the teleportation-based logical interconnect. The design goal of the the quantum logic array architecture is to illustrate a model for a large-scale quantum architecture that solves the primary challenges of system-level reliability and data distribution over large distances. The QLA's logical interconnect design, which employs the quantum repeater protocol, is in principle capable of supporting the communication requirements for applications as large as the factoring of a 2048-bit number using Shor's quantum factoring algorithm. Our physical-level assumptions and architectural component validations are based on the trapped ion technology for implementing quantum computing.
The assumption of maximum parallelism support for the successful realization of scalable quantum computers has led to homogeneous, "sea-of-qubits" architectures. The resulting architectures overcome the primary challenges of reliability and scalability at the cost of physically unacceptable system area. We find that by exploiting the natural serialization at both the application and the physical microarchitecture level of a quantum computer, we can reduce the area requirement while improving performance. In particular we present a scalable quantum architecture design that employs specialization of the system into memory and computational regions, each individually optimized to match hardware support to the available parallelism. Through careful application and system analysis, we find that our new architecture can yield up to a factor of thirteen savings in area due to specialization. In addition, by providing a memory hierarchy design for quantum computers, we can increase time performance by a factor of eight. This result brings us closer to the realization of a quantum processor that can solve meaningful problems.
This thesis addresses the design of a quantum computer (QC) architecture. Quantum error correction is a dominant factor as it is required to protect quantum bits (qubits) from decoherence. However, error correction's costs are substantial and call for a scale-up of 100X more qubits and instruction-level parallelism (ILP) on the order of 10,000 simultaneous operations per cycle. These are daunting challenges for a QC architect, who must balance demands in performance, control efficiency, and scalability of design. Error modeling is important for designing a QC so that error correction implementations and microarchitecture designs may be evaluated for effectiveness. This thesis presents a new deterministic approach to error modeling that is on the order of 1000X faster than previous Monte Carlo error models. While the deterministic error model is memory limited, it is capable of evaluating useful problems containing on the order of a dozen logical qubits encoded in the [[7,1,3]] quantum error correcting code (QECC). This dissertation presents a new QC processor architecture that leverages highly mobile qubits found in some QC technologies such as electron-spins on liquid helium (eSHe). The processor architecture presented here is designed to efficiently handle at least an order of magnitude more ILP than previously proposed designs, and it accommodates increasing ILP with size and latency costs scaling only linearly. Compilers are also crucial to a computer's performance and efficiency, and this dissertation describes new compiler optimizations including one that reduces hardware requirements by 25% with no performance loss. Multiple QC processors may be organized into a tiled configuration to provide sufficient ILP across the entire QC. This dissertation proposes a new distributed block tiling strategy that distributes encoded block qubits across arrays of data tiles and offloads non-critical path error correction routines to separate ancilla tiles. This strategy reduces tile capacity requirements by over 100X with the [[21,3,5]] QECC and achieves a simulated speedup of 2.8X for the eSHe QC when compared to the traditional tiling approach. In summary, this dissertation presents a novel QC architecture and design tools that improve performance and scalability while making efficient use of both control and qubit resources.
As the size of quantum systems becomes bigger, more complicated hardware is required to control these systems. In order to reduce the complexity, I discuss the amount of parallelism required for a fault-tolerant quantum computer and what computation speed can be achieved in different architectures. To build a large-scale quantum computer, one can use architectural principles, from classical computer architecture, like multiplexing or pipelining. In this document, a Quantum von Neumann architecture is introduced which uses specialized hardware for the different tasks of a quantum computer, like computation or storage. Furthermore, it requires long qubit coherence and the capability to move quantum information between the different parts of the quantum computer. As an example, a Quantum von Neumann architecture for trapped ions is presented which incorporates multiplexing in the memory region for large-scale quantum computation. To illustrate the capability of this architecture, a model trapped ion quantum computer based on Quantum von Neumann architecture, the Quantum 4004, is introduced. Its hardware is optimized for simplicity and uses the classical Intel 4004 CPU from 1971 as a blueprint. The Quantum 4004 has only a single processing zone and is structured in 4 qubit packages. Its quantum memory can store up to 32768 qubit ions and its computation speed is 10 μμμs for single qubit operations and 20 μμμs for two-qubit operations.