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ACM Journal on Emerging Technologies in Computing Systems

High-level interconnect model for the quantum logic array architecture

Tzvetan S. Metodi, Darshan Thaker, Andrew W. Cross, Isaac L. Chuang, Frederic T. Chong

Published Mar 1, 2008• 13 citations
Publisher

Abstract

We summarize the main characteristics of the quantum logic array (QLA) architecture with a careful look at the key issues not described in the original conference publications: primarily, the teleportation-based logical interconnect. The design goal of the the quantum logic array architecture is to illustrate a model for a large-scale quantum architecture that solves the primary challenges of system-level reliability and data distribution over large distances. The QLA's logical interconnect design, which employs the quantum repeater protocol, is in principle capable of supporting the communication requirements for applications as large as the factoring of a 2048-bit number using Shor's quantum factoring algorithm. Our physical-level assumptions and architectural component validations are based on the trapped ion technology for implementing quantum computing.

DOI
10.1145/1330521.1330522

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We summarize the main characteristics of the quantum logic array (QLA) architecture with a careful look at the key issues not described in the original conference publications: primarily, the teleportation-based logical interconnect. The design goal of the the quantum logic array architecture is to illustrate a model for a large-scale quantum architecture that solves the primary challenges of system-level reliability and data distribution over large distances. The QLA's logical interconnect design, which employs the quantum repeater protocol, is in principle capable of supporting the communication requirements for applications as large as the factoring of a 2048-bit number using Shor's quantum factoring algorithm. Our physical-level assumptions and architectural component validations are based on the trapped ion technology for implementing quantum computing.
Recent experimental advances have demonstrated technologies capable of supporting scalable quantum computation. A critical next step is how to put those technologies together into a scalable, fault-tolerant system that is also feasible. We propose a quantum logic array (QLA) microarchitecture that forms the foundation of such a system. The QLA focuses on the communication resources necessary to efficiently support fault-tolerant computations. We leverage the extensive groundwork in quantum error correction theory and provide analysis that shows that our system is both asymptotically and empirically fault tolerant. Specifically, we use the QLA to implement a hierarchical, array-based design and a logarithmic expense quantum-teleportation communication protocol. Our goal is to overcome the primary scalability challenges of reliability, communication, and quantum resource distribution that plague current proposals for large-scale quantum computing. Our work complements recent work by Balenseifer et al. (2005), which studies the software tool chain necessary to simplify development of quantum applications; here we focus on modeling a full-scale optimized microarchitecture for scalable computing.
Quantum computing is an emerging field that offers revolutionary and exciting new ways to process, store, and transport information. Moreover, realizing large-scale quantum systems requires advances in science and engineering that are now very close to reality. Such systems will need many classical and quantum parts that must fit together into one architecture, in which each component plays an integral role over the course of an application execution. Therefore, it is important that we draw upon the experiences gained from traditional architectures, to develop a model for a large-scale quantum system that provides the methodology necessary for the many different components to work together. In this thesis, I describe the design of the Quantum Logic Array (QLA) architecture, which tackles critical scalability issues such as the cost of error correction and distributing data over large-distances. To accurately model the performance of the QLA architecture—the ion-trap technology is used since every component necessary for universal quantum computation has been demonstrated in the laboratory. However, due to its design approach for maximizing parallelism, the QLA system suffers from large area overhead. To combat the area problem, I describe an architecture that uses the concept of hardware specialization employed in traditional architectures. The new architecture is based on the QLA model, but is divided into separately optimized quantum memory hierarchy and logic specific regions. The result is a scalable system design that exploits the available parallelism to balance both quantum and classical resources, while both reducing the area of the chip and increasing its performance.
We have created the architecture of a quantum multicomputer and analyzed its performance for running Shor’s algorithm for factoring large numbers. In this paper, we combine fault-tolerance techniques with performance goals for our architecture, which uses a linear interconnect and six logical qubits per node. Our performance target of factoring a 1,024-bit number in one month requires teleporting 6.2 logical qubits per second on each link in the system, which translates to 3,300 physical teleportations per second on each link. A qubus-based interconnect generates Bell pairs of intermediate fidelity that must be purified. Starting from a Bell state with fidelity F = 0.638, as a qubus-based cavity QED interconnect might generate with a qubit-to-qubit loss of 3.4dB, about 1.5 million physical entanglement attempts per second are enough to reach this level of performance.
Exploiting recent advances in quantum trapped-ion technologies, we propose a scalable, fault-tolerant quantum computing architecture that overcomes the fundamental challenges of building a full-scale quantum computer and leaves the fabrication a daunting but primarily an engineering concern. Using a hierarchical array-based design and a quantum teleportation communication protocol, we are able to overcome the primary scalability challenges of reliability, communication, and quantum resource distribution. In particular, we present a reconfigurable quantum circuit substrate, or "quantum FPGA'' (qFPGA) which allows efficient implementation of universal quantum gates and error correction. We use this qFPGA as a basic building block for an array structure that scalably provides communication channels and quantum resource distribution. We exploit a hierarchical combination of ballistic transport of data ions and quantum teleportation to reduce the cost of reliable communication from exponential to polynomial in distance. By using a set of simulation tools we are able to evaluate a hypothetical design of a future general purpose quantum computer and describe the execution of a fault-tolerant Toffoli gate construction. Without considering classical control constraints and assuming best-possible ion-trap parameters our computer consists of level 2 encoded qubits with the Steane \ecc code tightly connected by the teleportation interconnect, and capable of executing a fault-tolerant Toffoli gate in roughly 2.3 seconds. This translates to factoring a 128-bit number in slightly over 40 hours in circuits dominated by Toffoli gates.
Quantum computers will potentially be able to solve certain classes of problems more efficiently than possible on a classical computer. Due to the fragility of quantum data, a large scale quantum computer will require a robust system to enable reliable communication within the datapath. We present a scalable architecture for a quantum computer which specifically addresses communication concerns. Our design minimizes communication error by using a specialized interconnection network to perform long-distance movement. We developed a set of tools to construct and study quantum datapath designs based on ion trap quantum technology. Our tools automatically synthesize and insert the interconnection network used for long-distance communication into the target datapath. We present a set of greedy heuristics to optimize the routing and scheduling of communication within this network and show that our approach performs as well as an optimal case determined using integer linear programming. We study a number of different quantum circuits including randomly generated circuits, quantum adder circuits, and ultimately Shor's factorization algorithm and show that designs using our optimizations significantly improve upon prior work in terms of a probabilistic area delay metric.
Quantum computers will potentially be able to solve certain classes ofproblems more efficiently than possible on a classical computer. Dueto the fragility of quantum data, a large scale quantum computer willrequire a robust system to enable reliable communication within thedatapath. We present a scalable architecture for a quantum computerwhich specifically addresses communication concerns. Our designminimizes communication error by using a specialized interconnectionnetwork to perform long-distance movement.We developed a set of tools to construct and study quantum datapathdesigns based on ion trap quantum technology. Our tools automaticallysynthesize and insert the interconnection network used forlong-distance communication into the target datapath. We present aset of greedy heuristics to optimize the routing and scheduling ofcommunication within this network and show that our approach performsas well as an optimal case determined using integer linearprogramming. We study a number of different quantum circuitsincluding randomly generated circuits, quantum adder circuits, andultimately Shor's factorization algorithm and show that designs usingour optimizations significantly improve upon prior work in terms of aprobabilistic area delay metric.