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International Journal of Quantum Information

Research on error-correction algorithm of high-speed QKD system based on FPGA

Shi-Biao Tang, Jie Cheng

Published Mar 1, 2019• 2 citations
Publisher

Abstract

In the process of quantum key distribution (QKD), error correction algorithm is used to correct the error bits of the key at both ends. The existing applied QKD system has a low key rate and is generally Kbps of magnitude. Therefore, the performance requirement of data processing such as error correction is not high. In order to cope with the development demand of high-speed QKD system in the future, this paper introduces the Winnow algorithm to realize high-speed parity and hamming error correction based on Field Programmable Gate Array (FPGA), and explores the performance limit of this algorithm. FPGA hardware implementation can achieve the scale of Mbps bandwidth, with choosing different group length of sifted key by different error rate, and can achieve higher error correction efficiency by reducing the information leakage in the process of error correction, and improves the QKD system’s secure key rate, thus helping the future high-speed QKD system.

DOI
10.1142/s0219749919500138

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In the process of quantum key distribution (QKD), error correction algorithm is used to correct the error bits of the key at both ends. The existing applied QKD system has a low key rate and is generally Kbps of magnitude. Therefore, the performance requirement of data processing such as error correction is not high. In order to cope with the development demand of high-speed QKD system in the future, this paper introduces the Winnow algorithm to realize high-speed parity and hamming error correction based on Field Programmable Gate Array (FPGA), and explores the performance limit of this algorithm. FPGA hardware implementation can achieve the scale of Mbps bandwidth, with choosing different group length of sifted key by different error rate, and can achieve higher error correction efficiency by reducing the information leakage in the process of error correction, and improves the QKD system’s secure key rate, thus helping the future high-speed QKD system.
The contribution of this paper is implementing a high throughput LDPC codec in FPGA for quantum key distribution (QKD) system. By software, the throughput of error correction in QKD system via LDPC codec could only reach 1.8Mbps, which is not satisfactory for high speed QKD systems. Thus, it is desirable that LDPC error correction is realized in FPGA to increase the throughput. LDPC codec is implemented according to IEEE802.16e standard. The encoder directly uses a parity-check matrix of lower triangular structure without the construction of generator matrix, so that it effectively reduce the encoding complexity of Richardson encoding algorithm. The decoder uses the BP Min-Sum algorithm to balance performance and complexity. The codec is implemented in an Altera Arria II EP2AGX260 FPGA with a 2304-bit code length and 2/3 code rate. The partly parallel decoding structure achieves a 99.95 Mbps processing throughput on the condition that the maximum number of iterations for each code block is 20. The achievable throughput is much higher than the requirements of current QKD systems.
A real-time quantum key distribution (QKD) system is developed in this paper. In the system, based on the feature of a field-programmable gate array, secure key extraction control and algorithm have been optimally designed to perform sifting, error correction, and privacy amplification altogether in real time. In the QKD experiment, information synchronization mechanism and high-speed classic data channel are designed to ensure the steady operation of the system. Decoy state and synchronous laser light source are used in the system, while the length of optical fiber between Alice and Bob is 20 km. With photons repetition frequency of 20 MHz, the final key rate could reach 17 kb/s. Smooth and robust operation is verified with 6 h continuous test and associated with encrypted voice communication test.
For high-speed quantum key distribution systems, error reconciliation is often the bottleneck affecting system performance. By exchanging common information through a public channel, the identical key can be generated on both communicating sides. However, the necessity to eliminate disclosed bits for security reasons lowers the final key rate. To improve this key rate, the amount of disclosed bits should be minimized. In addition, decreasing the time spent on error reconciliation also improves the key rate. In this paper, we introduce a practical method for expeditious error reconciliation implemented in a field programmable gate array for a discrete variable quantum key distribution system, and illustrate the superiority of this method to other similar algorithms running on a PC. Experimental results demonstrate the rapidity of the proposed protocol.
For high-speed quantum key distribution (QKD) post processing, information reconciliation is the most computational step, which usually acts as the system speed bottleneck. Reconciliation efficiency and operation throughput are the two most important performance parameters, but they are often compromised to each other in actual realization due to the available hardware resources. Another characteristic of the information reconciliation is that its channel is time-varying, and in order to guarantee high efficiency, some rate-compatible error correction scheme should be adopted. To cope with the above problems, this paper proposes a rate-compatible high-efficiency reconciliation algorithm based on quasi-cyclic (QC) low-density parity-check (LDPC) codes and puncturing algorithms. On the other hand, in order to obtain high throughput while maintaining low implementation complexity, the normalized min-sum algorithm (NMSA) is realized and optimized by using the fast prototyping tool of high-level synthesis (HLS). The proposed information reconciliation module was implemented on the Xilinx Zynq Ultrascale+ ZCU102 development board. Experimental results show that the maximum throughput rate of the implemented reconciliation module in this paper can reach 136 Mbps, while the efficiency factor is kept lower than 1.32 across the error rate range of 1.7%∼10.6% under the remaining frame error rate level of 10−3. The comprehensive good performance obtained by our design can strongly support the development of modern high-speed QKD systems.
Quantum Key Distribution (QKD) technique has drawn many attentions because it can generate and distribute cryptographic keys with provable information theoretic security. To achieve a high secure key rate, it is a developing trend to adopt the FPGA-based scheme. Sifting is an important processing module of QKD post processing system (QKDPPS) and its communication traffic and input data rate are much larger than other modules of QKDPPS. In this paper, a FPGA-based design of efficient QKD sifting module is presented. To reduce the interaction data amount and thus increase the secure key rate, a high compression ratio round-length based compression encoder and decoder are designed in the sifting modules of two parties. To accelerate the processing speed and thus increase the secure key rate, parallelized processing scheme is designed. The experimental results demonstrate the feasibility and efficiency of the sifting module.
Abstract This paper presents a new hardware implementation of the quantum key distributed cryptography protocol using Field Programmable Gate Array (FPGA). In many security applications, the software implementations of key distribution algorithms are slow and inefficient. In order to solve this problems, new hardware architecture was proposed to speed up the performance and flexibility of key distribution algorithms. The concurrent computing designs quantum key distribution protocol with reducing the hardware area, producing a high throughput and low latency. It also showed high speed processing and consumed low power. An efficient hardware architectural model for quantum key distribution protocol was developed using very high-speed integrated circuit hardware description language (VHDL). This hardware designed to be used with any quantum key distribution protocol to distribution the secret key securely. The hardware implemented and test with Spartan-3 FPGA board and the results show a throughput of 8 Mbps and efficiency of 1.6 Mbps/slice.