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Journal of Lightwave Technology

A Code Rate-Compatible High-Throughput Hardware Implementation Scheme for QKD Information Reconciliation

Ming Bo Zhu, Ke Cui, Simeng Li, Lei Kong, Shi-Biao Tang, Jian Sun

Published Feb 8, 2022• 11 citations
Publisher

Abstract

For high-speed quantum key distribution (QKD) post processing, information reconciliation is the most computational step, which usually acts as the system speed bottleneck. Reconciliation efficiency and operation throughput are the two most important performance parameters, but they are often compromised to each other in actual realization due to the available hardware resources. Another characteristic of the information reconciliation is that its channel is time-varying, and in order to guarantee high efficiency, some rate-compatible error correction scheme should be adopted. To cope with the above problems, this paper proposes a rate-compatible high-efficiency reconciliation algorithm based on quasi-cyclic (QC) low-density parity-check (LDPC) codes and puncturing algorithms. On the other hand, in order to obtain high throughput while maintaining low implementation complexity, the normalized min-sum algorithm (NMSA) is realized and optimized by using the fast prototyping tool of high-level synthesis (HLS). The proposed information reconciliation module was implemented on the Xilinx Zynq Ultrascale+ ZCU102 development board. Experimental results show that the maximum throughput rate of the implemented reconciliation module in this paper can reach 136 Mbps, while the efficiency factor is kept lower than 1.32 across the error rate range of 1.7%∼10.6% under the remaining frame error rate level of 10−3. The comprehensive good performance obtained by our design can strongly support the development of modern high-speed QKD systems.

DOI
10.1109/jlt.2022.3149567

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For high-speed quantum key distribution (QKD) post processing, information reconciliation is the most computational step, which usually acts as the system speed bottleneck. Reconciliation efficiency and operation throughput are the two most important performance parameters, but they are often compromised to each other in actual realization due to the available hardware resources. Another characteristic of the information reconciliation is that its channel is time-varying, and in order to guarantee high efficiency, some rate-compatible error correction scheme should be adopted. To cope with the above problems, this paper proposes a rate-compatible high-efficiency reconciliation algorithm based on quasi-cyclic (QC) low-density parity-check (LDPC) codes and puncturing algorithms. On the other hand, in order to obtain high throughput while maintaining low implementation complexity, the normalized min-sum algorithm (NMSA) is realized and optimized by using the fast prototyping tool of high-level synthesis (HLS). The proposed information reconciliation module was implemented on the Xilinx Zynq Ultrascale+ ZCU102 development board. Experimental results show that the maximum throughput rate of the implemented reconciliation module in this paper can reach 136 Mbps, while the efficiency factor is kept lower than 1.32 across the error rate range of 1.7%∼10.6% under the remaining frame error rate level of 10−3. The comprehensive good performance obtained by our design can strongly support the development of modern high-speed QKD systems.
In continuous-variable (CV) quantum key distribution (QKD), the reconciliation efficiency and frame error rate of the information reconciliation have a significant impact on the secret key rate. For a fixed-rate multiedge-type low-density parity-check (LDPC) code, the reconciliation efficiency and frame error rate will inevitably vary due to the fluctuations of the signal-to-noise ratio (SNR) of the CV QKD system, which degrades the performance of the system. We propose a high-efficiency rate-adaptive information reconciliation scheme by combining raptorlike (RL) LDPC codes with the addition of trusted noises. We establish the model of adding trusted noises and combine it with the RL LDPC codes to optimize the secret key rate under the time-varying channel. The simulation results show that our scheme can maintain a high reconciliation efficiency of more than 94.4% and a low frame error rate within 15% fluctuation range of the SNR. Furthermore, we implement the hardware acceleration of the proposed rate-adaptive scheme on a graphics processing unit and achieve a decoding throughput of 65.5 Mbits/s by optimizing the storage of the parity-check matrix. Our results are useful for the practical CV QKD under the realistic time-varying channel.
Although quantum key distribution (QKD) comes from the development of quantum theory, the implementation of a practical QKD system does involve a lot of classical process, such as key reconciliation and privacy amplification, which is called post-processing. Post-processing has been a crucial element to high speed QKD systems, even the bottleneck of it because of its relatively high time consumption. Low density parity check (LDPC) is now becoming a promising approach of overcoming the bottleneck due to its good performance in processing throughput. In this article we propose and simulate an easily implemented but efficiently rate-adaptive LDPC coding approach of reconciliation, different from the previously proposed puncturing- and shortening-based approach. We also give a measure for choosing the optimal LDPC parameter for our rate-adaptive approach according to error rates.
Information reconciliation is a crucial procedure in the classical post-processing of quantum key distribution (QKD). Poor reconciliation efficiency, revealing more information than strictly needed, may compromise the maximum attainable distance, while poor performance of the algorithm limits the practical throughput in a QKD device. Historically, reconciliation has been mainly done using close to minimal information disclosure but heavily interactive procedures, like \textit{Cascade}, or using less efficient but also less interactive ---just one message is exchanged--- procedures, like the ones based in low-density parity-check (LDPC) codes. The price to pay in the LDPC case is that good efficiency is only attained for very long codes and in a very narrow range centered around the quantum bit error rate (QBER) that the code was designed to reconcile, thus forcing to have several codes if a broad range of QBER needs to be catered for. Real world implementations of these methods are thus very demanding, either on computational or communication resources or both, to the extent that the last generation of GHz clocked QKD systems are finding a bottleneck in the classical part. In order to produce compact, high performance and reliable QKD systems it would be highly desirable to remove these problems. Here we analyse the use of short-length LDPC codes in the information reconciliation context using a low interactivity, \textit{blind}, protocol that avoids an a priori error rate estimation. We demonstrate that 2×1032 \times 10^32×103 bits length LDPC codes are suitable for blind reconciliation. Such codes are of high interest in practice, since they can be used for hardware implementations with very high throughput.
The contribution of this paper is implementing a high throughput LDPC codec in FPGA for quantum key distribution (QKD) system. By software, the throughput of error correction in QKD system via LDPC codec could only reach 1.8Mbps, which is not satisfactory for high speed QKD systems. Thus, it is desirable that LDPC error correction is realized in FPGA to increase the throughput. LDPC codec is implemented according to IEEE802.16e standard. The encoder directly uses a parity-check matrix of lower triangular structure without the construction of generator matrix, so that it effectively reduce the encoding complexity of Richardson encoding algorithm. The decoder uses the BP Min-Sum algorithm to balance performance and complexity. The codec is implemented in an Altera Arria II EP2AGX260 FPGA with a 2304-bit code length and 2/3 code rate. The partly parallel decoding structure achieves a 99.95 Mbps processing throughput on the condition that the maximum number of iterations for each code block is 20. The achievable throughput is much higher than the requirements of current QKD systems.
In a continuous-variable quantum key distribution (CV-QKD) system, the computation speed of the post-processing procedure, including information reconciliation (IR) and privacy amplification (PA), inevitably affects the practical secret key rate. IR and PA can be implemented in parallel using low-density parity-check (LDPC) codes and hash functions, respectively. We achieve high-speed hardware-accelerated post-processing procedure for Gaussian symbols on a field-programmable gate array (FPGA) by taking advantage of its superior parallel processing ability. To this end, the sum-product algorithm decoders and a modified LDPC codes construction algorithm adapted to FPGA's characteristics are developed and employed. Two different structures including multiplexing and non-multiplexing are designed to achieve the trade-off between the speed and area of FPGAs, so that an optimal scheme can be adopted according to the requirement of a practical system. Simulation results show that the maximum throughput can reach 100 M symbols/s. We verified the correctness of the post-processing procedures when implemented on the Xilinx VC709 evaluation board, which is populated with the Virtex-7 XC7VX690T FPGA and provided some possible solutions to obtain better performance when more advanced FPGAs are available. The scheme can be applied readily for real-time key extraction and effectively reduce power consumption of the CV-QKD system.
Quantum key distribution (QKD), based on quantum mechanics, enables unconditionally secure key exchange even against adversaries with unlimited computing power. As the core of QKD post-processing, information reconciliation (IR) and privacy amplification (PA) ensure key consistency and security by correcting errors and removing leaked information. With the trend toward miniaturized and chip-based QKD systems, post-processing modules require highly integrated designs. FPGAs offer an ideal solution due to their low cost, power efficiency, and flexibility. This paper presents an FPGA-based QKD post-processing architecture using a polar codes-based appending IR algorithm, achieving reconciliation efficiency better than 1.1 under Eµ≥ 0.06 and Rm= 4. A convolution-structured Toeplitz hash module is developed for PA, supporting 53.13 Mbps data rate and 26.45 Mbps key rate with RPA= 0.5. The complete system is implemented on a Xilinx XCKU040 FPGA. Experimental results show support for 176.58 Mbps input, 36.59 Mbps real-time processing, and 17.56 Mbps key output, demonstrating strong performance and engineering suitability. The design features high integration and portability, offering a practical hardware solution for efficient QKD post-processing.