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IEEE International Conference on Solid-State and Integrated Circuit Technology

Implementation of a high throughput LDPC codec in FPGA for QKD system

Cong Hui, Yonggang Wang, Xiao-Ming Lu

Published Oct 1, 2016• 6 citations
Publisher

Abstract

The contribution of this paper is implementing a high throughput LDPC codec in FPGA for quantum key distribution (QKD) system. By software, the throughput of error correction in QKD system via LDPC codec could only reach 1.8Mbps, which is not satisfactory for high speed QKD systems. Thus, it is desirable that LDPC error correction is realized in FPGA to increase the throughput. LDPC codec is implemented according to IEEE802.16e standard. The encoder directly uses a parity-check matrix of lower triangular structure without the construction of generator matrix, so that it effectively reduce the encoding complexity of Richardson encoding algorithm. The decoder uses the BP Min-Sum algorithm to balance performance and complexity. The codec is implemented in an Altera Arria II EP2AGX260 FPGA with a 2304-bit code length and 2/3 code rate. The partly parallel decoding structure achieves a 99.95 Mbps processing throughput on the condition that the maximum number of iterations for each code block is 20. The achievable throughput is much higher than the requirements of current QKD systems.

DOI
10.1109/icsict.2016.7998780

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The contribution of this paper is implementing a high throughput LDPC codec in FPGA for quantum key distribution (QKD) system. By software, the throughput of error correction in QKD system via LDPC codec could only reach 1.8Mbps, which is not satisfactory for high speed QKD systems. Thus, it is desirable that LDPC error correction is realized in FPGA to increase the throughput. LDPC codec is implemented according to IEEE802.16e standard. The encoder directly uses a parity-check matrix of lower triangular structure without the construction of generator matrix, so that it effectively reduce the encoding complexity of Richardson encoding algorithm. The decoder uses the BP Min-Sum algorithm to balance performance and complexity. The codec is implemented in an Altera Arria II EP2AGX260 FPGA with a 2304-bit code length and 2/3 code rate. The partly parallel decoding structure achieves a 99.95 Mbps processing throughput on the condition that the maximum number of iterations for each code block is 20. The achievable throughput is much higher than the requirements of current QKD systems.
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As the continuously increasing demand of high data rate and lower transmission, many modern communication systems employ the LDPC coding scheme with ultra-high throughput decoder to achieve these challenging requirements. However, due to the implementation complexity of decoding algorithm, designing an ultra-high throughput decoder of LDPC codes still suffers many difficulties. Therefore, we propose a FPGA-based LDPC decoder with partial parallel decoding, which splits and virtually supplements the parity-check matrix to achieve higher throughput and lower latency. Our proposed FPGA-based decoder can achieve a throughput of 6.072Gbps in 10 iterations for the highest rate 5G-LDPC code.
For high-speed quantum key distribution (QKD) post processing, information reconciliation is the most computational step, which usually acts as the system speed bottleneck. Reconciliation efficiency and operation throughput are the two most important performance parameters, but they are often compromised to each other in actual realization due to the available hardware resources. Another characteristic of the information reconciliation is that its channel is time-varying, and in order to guarantee high efficiency, some rate-compatible error correction scheme should be adopted. To cope with the above problems, this paper proposes a rate-compatible high-efficiency reconciliation algorithm based on quasi-cyclic (QC) low-density parity-check (LDPC) codes and puncturing algorithms. On the other hand, in order to obtain high throughput while maintaining low implementation complexity, the normalized min-sum algorithm (NMSA) is realized and optimized by using the fast prototyping tool of high-level synthesis (HLS). The proposed information reconciliation module was implemented on the Xilinx Zynq Ultrascale+ ZCU102 development board. Experimental results show that the maximum throughput rate of the implemented reconciliation module in this paper can reach 136 Mbps, while the efficiency factor is kept lower than 1.32 across the error rate range of 1.7%∼10.6% under the remaining frame error rate level of 10−3. The comprehensive good performance obtained by our design can strongly support the development of modern high-speed QKD systems.
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The throughput of error correction is one of the main bottlenecks of high-speed continuous variable quantum key distribution (CV-QKD) post-processing, which directly restricts the practical secret key rates (SKR). Implementing the decoder of low-density parity-check (LDPC) codes based on FPGA in limited precision can improve the decoding throughput significantly. In this paper, a high-throughput decoder architecture with limited precision for quasi-cyclic LDPC (QC-LDPC) codes is proposed. In particular, decoding of two typical LDPC codes, with code rates 0.2 and 0.1, for CV-QKD have been implemented on a commercial FPGA. The clock operates at 100 MHZ and the throughput of 1.44 Gbps and 0.78 Gbps is achieved, respectively, which can support 71.89 Mbps and 9.97 Mbps real-time SKR under transmission distance of 25 km and 50 km, respectively. The proposed architecture paves the way for high-rate real-time CV-QKD deployment in secure metropolitan area network.
Non-Binary Low-Density-Parity-Check codes (NB-LDPC) have shown superior performance but its huge complexity and low throughput prevent it from practical applications. This paper presents a novel architecture to implement a kind of high-throughput low-complexity irregular quasi-cyclic NB-LDPC decoder over GF (16) based on Extended Min-Sum (EMS) Algorithm. Double clocks are adopted in this paper. The low frequency clock at 60 MHz serves as the system clock and the high frequency clock at 480 MHz works for check nodes and variable nodes thus they can be reused 8 times during one system clock period as a result the complexity can be largely reduced. Synthesis result shows that the throughput can achieve 68.57 Mbps at 5 iterations. FPGA testing result shows that the decoder has little performance degradation compared with its floating model and it can provide about 0.5 dB coding gain compared with its binary LDPC code of the same block length. The proposed architecture can be conveniently extended to higher Galois Filed such as GF (64) or GF (256) and it can be applied for different code length and rate by modifying a slight part of the decoder. Compared with previous works, the decoder proposed in this paper is more efficient for practical applications.